Loading drivers/irqchip/irq-xtensa-mx.c +20 −14 Original line number Diff line number Diff line Loading @@ -72,14 +72,17 @@ static void xtensa_mx_irq_mask(struct irq_data *d) if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - HW_IRQ_MX_BASE), MIENG); } else { unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq); if (ext_irq >= HW_IRQ_MX_BASE) { set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG); return; } } mask = __this_cpu_read(cached_irq_mask) & ~mask; __this_cpu_write(cached_irq_mask, mask); xtensa_set_sr(mask, intenable); } } static void xtensa_mx_irq_unmask(struct irq_data *d) { Loading @@ -87,14 +90,17 @@ static void xtensa_mx_irq_unmask(struct irq_data *d) if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - HW_IRQ_MX_BASE), MIENGSET); } else { unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq); if (ext_irq >= HW_IRQ_MX_BASE) { set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET); return; } } mask |= __this_cpu_read(cached_irq_mask); __this_cpu_write(cached_irq_mask, mask); xtensa_set_sr(mask, intenable); } } static void xtensa_mx_irq_enable(struct irq_data *d) { Loading Loading
drivers/irqchip/irq-xtensa-mx.c +20 −14 Original line number Diff line number Diff line Loading @@ -72,14 +72,17 @@ static void xtensa_mx_irq_mask(struct irq_data *d) if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - HW_IRQ_MX_BASE), MIENG); } else { unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq); if (ext_irq >= HW_IRQ_MX_BASE) { set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENG); return; } } mask = __this_cpu_read(cached_irq_mask) & ~mask; __this_cpu_write(cached_irq_mask, mask); xtensa_set_sr(mask, intenable); } } static void xtensa_mx_irq_unmask(struct irq_data *d) { Loading @@ -87,14 +90,17 @@ static void xtensa_mx_irq_unmask(struct irq_data *d) if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - HW_IRQ_MX_BASE), MIENGSET); } else { unsigned int ext_irq = xtensa_get_ext_irq_no(d->hwirq); if (ext_irq >= HW_IRQ_MX_BASE) { set_er(1u << (ext_irq - HW_IRQ_MX_BASE), MIENGSET); return; } } mask |= __this_cpu_read(cached_irq_mask); __this_cpu_write(cached_irq_mask, mask); xtensa_set_sr(mask, intenable); } } static void xtensa_mx_irq_enable(struct irq_data *d) { Loading