Commit eafcbb68 authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Add core event list for Alderlake-N 

Alderlake-N only has E-core, it has been moved to non-hybrid code path on
the kernel side, so add the cpuid for Alderlake-N separately.

Add core event list for Alderlake-N, it is based on the
ADL gracemont v1.16 JSON file.

https://github.com/intel/perfmon/tree/main/ADL/events/



Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221124031441.110134-1-zhengjun.xing@linux.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 765d4e49

tools/perf/pmu-events/arch/x86/alderlaken/cache.json

0 → 100644
+330 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.MISS",

        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",

        "SampleAfterValue": "200003",

        "UMask": "0x41"

    },

    {

        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",

        "EventCode": "0x2e",

        "EventName": "LONGEST_LAT_CACHE.REFERENCE",

        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",

        "SampleAfterValue": "200003",

        "UMask": "0x4f"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.IFETCH",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",

        "SampleAfterValue": "200003",

        "UMask": "0x38"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).",

        "SampleAfterValue": "200003",

        "UMask": "0x20"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.",

        "SampleAfterValue": "200003",

        "UMask": "0x8"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",

        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",

        "SampleAfterValue": "200003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.LOAD",

        "SampleAfterValue": "200003",

        "UMask": "0x7"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",

        "SampleAfterValue": "200003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",

        "SampleAfterValue": "200003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",

        "EventCode": "0x34",

        "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",

        "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",

        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x80"

    },

    {

        "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",

        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",

        "Data_LA": "1",

        "EventCode": "0xd1",

        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.",

        "EventCode": "0x04",

        "EventName": "MEM_SCHEDULER_BLOCK.ALL",

        "SampleAfterValue": "20003",

        "UMask": "0x7"

    },

    {

        "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",

        "EventCode": "0x04",

        "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",

        "SampleAfterValue": "20003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",

        "EventCode": "0x04",

        "EventName": "MEM_SCHEDULER_BLOCK.RSV",

        "SampleAfterValue": "20003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",

        "EventCode": "0x04",

        "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",

        "SampleAfterValue": "20003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of load uops retired.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",

        "PEBS": "1",

        "PublicDescription": "Counts the total number of load uops retired.",

        "SampleAfterValue": "200003",

        "UMask": "0x81"

    },

    {

        "BriefDescription": "Counts the number of store uops retired.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",

        "PEBS": "1",

        "PublicDescription": "Counts the total number of store uops retired.",

        "SampleAfterValue": "200003",

        "UMask": "0x82"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x80",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x10",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x100",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x20",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x4",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x200",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x40",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",

        "MSRIndex": "0x3F6",

        "MSRValue": "0x8",

        "PEBS": "2",

        "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x5"

    },

    {

        "BriefDescription": "Counts the number of retired split load uops.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",

        "PEBS": "1",

        "SampleAfterValue": "200003",

        "UMask": "0x41"

    },

    {

        "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",

        "Data_LA": "1",

        "EventCode": "0xd0",

        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",

        "PEBS": "2",

        "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.",

        "SampleAfterValue": "1000003",

        "UMask": "0x6"

    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F803C0001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x4003C0001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x8003C0001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_HIT",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F803C0002",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x10003C0002",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",

        "EventCode": "0x71",

        "EventName": "TOPDOWN_FE_BOUND.ICACHE",

        "SampleAfterValue": "1000003",

        "UMask": "0x20"

    }

]

tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json

0 → 100644
+18 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",

        "SampleAfterValue": "20003",

        "UMask": "0x4"

    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",

        "EventCode": "0xc2",

        "EventName": "UOPS_RETIRED.FPDIV",

        "PEBS": "1",

        "SampleAfterValue": "2000003",

        "UMask": "0x8"

    }

]

tools/perf/pmu-events/arch/x86/alderlaken/frontend.json

0 → 100644
+26 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",

        "EventCode": "0xe6",

        "EventName": "BACLEARS.ANY",

        "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend.  Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",

        "EventCode": "0x80",

        "EventName": "ICACHE.ACCESSES",

        "PublicDescription": "Counts the total number of requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",

        "UMask": "0x3"

    },

    {

        "BriefDescription": "Counts the number of instruction cache misses.",

        "EventCode": "0x80",

        "EventName": "ICACHE.MISSES",

        "PublicDescription": "Counts the number of missed requests to the instruction cache.  The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one.  Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",

        "SampleAfterValue": "200003",

        "UMask": "0x2"

    }

]

tools/perf/pmu-events/arch/x86/alderlaken/memory.json

0 → 100644
+81 −0
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.ANY_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xff"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.L1_BOUND_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xf4"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.OTHER_AT_RET",

        "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",

        "SampleAfterValue": "1000003",

        "UMask": "0xc0"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.PGWALK_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0xa0"

    },

    {

        "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",

        "EventCode": "0x05",

        "EventName": "LD_HEAD.ST_ADDR_AT_RET",

        "SampleAfterValue": "1000003",

        "UMask": "0x84"

    },

    {

        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",

        "SampleAfterValue": "20003",

        "UMask": "0x2"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400001",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400002",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    },

    {

        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",

        "EventCode": "0xB7",

        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",

        "MSRIndex": "0x1a6,0x1a7",

        "MSRValue": "0x3F84400002",

        "SampleAfterValue": "100003",

        "UMask": "0x1"

    }

]

tools/perf/pmu-events/arch/x86/alderlaken/other.json

0 → 100644
+38 −0

File added.

Preview size limit exceeded, changes collapsed.