Commit eaf87e56 authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno Committed by Stephen Boyd
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clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d 



In the previous commit ("clk: qcom: rcg2: Stop hardcoding gfx3d pingpong
parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops) were
generalized in order to be able to reuse the same ops for more than just
one clock for one SoC: follow the change here in the MSM8996 MMCC.

Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210113183817.447866-7-angelogioacchino.delregno@somainline.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 7cbb78a9

drivers/clk/qcom/mmcc-msm8996.c

+18 −11
Original line number Diff line number Diff line
@@ -528,7 +528,8 @@ static struct clk_rcg2 maxi_clk_src = { 
	},

};



static struct clk_rcg2 gfx3d_clk_src = {

static struct clk_rcg2_gfx3d gfx3d_clk_src = {

	.rcg = {

		.cmd_rcgr = 0x4000,

		.hid_width = 5,

		.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
@@ -539,6 +540,12 @@ static struct clk_rcg2 gfx3d_clk_src = { 
			.ops = &clk_gfx3d_ops,

			.flags = CLK_SET_RATE_PARENT,

		},

	},

	.hws = (struct clk_hw*[]) {

		&mmpll9.clkr.hw,

		&mmpll2.clkr.hw,

		&mmpll8.clkr.hw

	},

};



static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
@@ -3089,7 +3096,7 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = { 
	[AHB_CLK_SRC] = &ahb_clk_src.clkr,

	[AXI_CLK_SRC] = &axi_clk_src.clkr,

	[MAXI_CLK_SRC] = &maxi_clk_src.clkr,

	[GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,

	[GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,

	[RBBMTIMER_CLK_SRC] = &rbbmtimer_clk_src.clkr,

	[ISENSE_CLK_SRC] = &isense_clk_src.clkr,

	[RBCPR_CLK_SRC] = &rbcpr_clk_src.clkr,