Commit eae23318 authored by Vladimir Stempen's avatar Vladimir Stempen Committed by Alex Deucher
Browse files

drm/amd/display: properly configure DCFCLK when enable/disable Freesync 



[Why]
Bandwidth validation is using Freesync parameters
from previous Freesync state.
Bandwidth validation ignores DCFCLK calculated
after Freesync parameters are configured

[How]
Set Freesync bandwidth parameters to its default
state before running bandwidth validation.
Take DCFCLK calculated after Freesync bandwidth
parameters are assigned and bandwidth is
recalculated.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Reviewed-by: default avatarNevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarVladimir Stempen <vladimir.stempen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 99243fd1

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+7 −0
Original line number Diff line number Diff line
@@ -1805,6 +1805,13 @@ bool dcn32_validate_bandwidth(struct dc *dc, 
	int pipe_cnt = 0;

	display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);

	struct mall_temp_config mall_temp_config;



	/* To handle Freesync properly, setting FreeSync DML parameters

	 * to its default state for the first stage of validation

	 */

	context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false;

	context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;



	DC_LOGGER_INIT(dc->ctx->logger);



	/* For fast validation, there are situations where a shallow copy of

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+6 −1
Original line number Diff line number Diff line
@@ -1769,6 +1769,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
	int i, pipe_idx, vlevel_temp = 0;

	double dcfclk = dcn3_2_soc.clock_limits[0].dcfclk_mhz;

	double dcfclk_from_validation = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

	double dcfclk_from_fw_based_mclk_switching = dcfclk_from_validation;

	bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=

			dm_dram_clock_change_unsupported;

	unsigned int dummy_latency_index = 0;
@@ -1804,7 +1805,7 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
					dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

			dcn32_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, false);

			maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;

			dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

			dcfclk_from_fw_based_mclk_switching = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];

			pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] !=

					dm_dram_clock_change_unsupported;

		}
@@ -1890,6 +1891,10 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
	pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_validation;

	pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;



	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {

		pipes[0].clks_cfg.dcfclk_mhz = dcfclk_from_fw_based_mclk_switching;

	}



	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {

		min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;

		min_dram_speed_mts_margin = 160;