Commit ea7db710 authored by Kan Liang's avatar Kan Liang Committed by Yunying Sun
Browse files

perf/x86/intel: Add Granite Rapids 

mainline inclusion
from mainline-v6.4-rc1
commit bc4000fd
category: feature
feature: GNR core PMU
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RV41
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=bc4000fdb009a531fc5b94339f8531eee64bc232



Intel-SIG: commit bc4000fd perf/x86/intel: Add Granite Rapids
Backport Granite Rapids core PMU support to kernel 5.10.

-------------------------------------

From core PMU's perspective, Granite Rapids is similar to the Sapphire
Rapids. The key differences include:

 - Doesn't need the AUX event workaround for the mem load event.
   (Implement in this patch).

 - Support Retire Latency (Has been implemented in the commit
   c87a3109 ("perf/x86: Support Retire Latency"))

 - The event list, which will be supported in the perf tool later.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20230314170041.2967712-1-kan.liang@linux.intel.com


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
parent ee181715

arch/x86/events/intel/core.c

+14 −2
Original line number Diff line number Diff line
@@ -5139,6 +5139,15 @@ pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 
	return x86_pmu.pebs ? attr->mode : 0;

}



static umode_t

mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)

{

	if (attr == &event_attr_mem_ld_aux.attr.attr)

		return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;



	return pebs_is_visible(kobj, attr, i);

}



static umode_t

lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)

{
@@ -5166,7 +5175,7 @@ static struct attribute_group group_events_td = { 


static struct attribute_group group_events_mem = {

	.name       = "events",

	.is_visible = pebs_is_visible,

	.is_visible = mem_is_visible,

};



static struct attribute_group group_events_tsx = {
@@ -5792,6 +5801,10 @@ __init int intel_pmu_init(void) 


	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

		fallthrough;

	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:

		pmem = true;

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -5808,7 +5821,6 @@ __init int intel_pmu_init(void) 
		x86_pmu.flags |= PMU_FL_NO_HT_SHARING;

		x86_pmu.flags |= PMU_FL_PEBS_ALL;

		x86_pmu.flags |= PMU_FL_INSTR_LATENCY;

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;



		x86_pmu.hw_config = hsw_hw_config;

		x86_pmu.get_event_constraints = spr_get_event_constraints;