Commit ea6e3c31 authored by Frank Wunderlich's avatar Frank Wunderlich Committed by Chun-Kuang Hu
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dt-bindings: mediatek: add mt7623 display-nodes



mt7623 uses mt2701/mt8173 for drm, but have own compatibles

Signed-off-by: default avatarFrank Wunderlich <frank-w@public-files.de>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarChun-Kuang Hu <chunkuang.hu@kernel.org>
parent 9123e3a7
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+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ Required properties (all function blocks):
	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
	"mediatek,<chip>-disp-mutex" 		- display mutex
	"mediatek,<chip>-disp-od"    		- overdrive
  the supported chips are mt2701, mt2712 and mt8173.
  the supported chips are mt2701, mt7623, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
  merge and split function blocks).
+1 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ output bus.

Required properties:
- compatible: "mediatek,<chip>-dpi"
  the supported chips are mt2701 , mt8173 and mt8183.
  the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
+2 −2
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@@ -7,7 +7,7 @@ channel output.

Required properties:
- compatible: "mediatek,<chip>-dsi"
  the supported chips are mt2701, mt8173 and mt8183.
- the supported chips are mt2701, mt7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY.

Required properties:
- compatible: "mediatek,<chip>-mipi-tx"
  the supported chips are mt2701, mt8173 and mt8183.
- the supported chips are mt2701, 7623, mt8173 and mt8183.
- reg: Physical base address and length of the controller's registers
- clocks: PLL reference clock
- clock-output-names: name of the output clock line to the DSI encoder
+4 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ its parallel input.

Required properties:
- compatible: Should be "mediatek,<chip>-hdmi".
- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clocks
@@ -32,6 +33,7 @@ The HDMI CEC controller handles hotplug detection and CEC communication.

Required properties:
- compatible: Should be "mediatek,<chip>-cec"
- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- interrupts: The interrupt signal from the function block.
- clocks: device clock
@@ -44,6 +46,7 @@ The Mediatek's I2C controller is used to interface with I2C devices.

Required properties:
- compatible: Should be "mediatek,<chip>-hdmi-ddc"
- the supported chips are mt7623 and mt8173
- reg: Physical base address and length of the controller's registers
- clocks: device clock
- clock-names: Should be "ddc-i2c".
@@ -56,6 +59,7 @@ output and drives the HDMI pads.

Required properties:
- compatible: "mediatek,<chip>-hdmi-phy"
- the supported chips are mt2701, mt7623 and mt8173
- reg: Physical base address and length of the module's registers
- clocks: PLL reference clock
- clock-names: must contain "pll_ref"