Commit ea6490b0 authored by Lucas Stach's avatar Lucas Stach Committed by Marek Vasut
Browse files

drm/bridge: tc358767: increase CLRSIPO count 



The current CLRSIPO count is marginal and does not work with high
DSI clock rates. Increase it a bit to allow the DSI link to work at
up to 1Gbps lane speed.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Tested-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220706132812.2171250-2-l.stach@pengutronix.de
parent 5fa9e161

drivers/gpu/drm/bridge/tc358767.c

+4 −4
Original line number Diff line number Diff line
@@ -1258,10 +1258,10 @@ static int tc_dsi_rx_enable(struct tc_data *tc) 
	u32 value;

	int ret;



	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 3);

	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 3);

	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 3);

	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 3);

	regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5);

	regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5);

	regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5);

	regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5);

	regmap_write(tc->regmap, PPI_D0S_ATMR, 0);

	regmap_write(tc->regmap, PPI_D1S_ATMR, 0);

	regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);