Commit ea5ed0f0 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-800Gbps-support' 



Petr Machata says:

====================
net: Add support for 800Gbps speed

Amit Cohen <amcohen@nvidia.com> writes:

The next Nvidia Spectrum ASIC will support 800Gbps speed.
The IEEE 802 LAN/MAN Standards Committee already published standards for
800Gbps, see the last update [1] and the list of approved changes [2].

As first phase, add support for 800Gbps over 8 lanes (100Gbps/lane).
In the future 800Gbps over 4 lanes can be supported also.

Extend ethtool to support the relevant PMDs and extend mlxsw and bonding
drivers to support 800Gbps.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents c1aa0a90 41305d37

drivers/net/bonding/bond_3ad.c

+9 −0
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ enum ad_link_speed_type { 
	AD_LINK_SPEED_100000MBPS,

	AD_LINK_SPEED_200000MBPS,

	AD_LINK_SPEED_400000MBPS,

	AD_LINK_SPEED_800000MBPS,

};



/* compare MAC addresses */
@@ -251,6 +252,7 @@ static inline int __check_agg_selection_timer(struct port *port) 
 *     %AD_LINK_SPEED_100000MBPS

 *     %AD_LINK_SPEED_200000MBPS

 *     %AD_LINK_SPEED_400000MBPS

 *     %AD_LINK_SPEED_800000MBPS

 */

static u16 __get_link_speed(struct port *port)

{
@@ -326,6 +328,10 @@ static u16 __get_link_speed(struct port *port) 
			speed = AD_LINK_SPEED_400000MBPS;

			break;



		case SPEED_800000:

			speed = AD_LINK_SPEED_800000MBPS;

			break;



		default:

			/* unknown speed value from ethtool. shouldn't happen */

			if (slave->speed != SPEED_UNKNOWN)
@@ -753,6 +759,9 @@ static u32 __get_agg_bandwidth(struct aggregator *aggregator) 
		case AD_LINK_SPEED_400000MBPS:

			bandwidth = nports * 400000;

			break;

		case AD_LINK_SPEED_800000MBPS:

			bandwidth = nports * 800000;

			break;

		default:

			bandwidth = 0; /* to silence the compiler */

		}

drivers/net/ethernet/mellanox/mlxsw/reg.h

+1 −0
Original line number Diff line number Diff line
@@ -4620,6 +4620,7 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2		BIT(10)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4		BIT(12)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8				BIT(15)

#define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8				BIT(19)



/* reg_ptys_ext_eth_proto_cap

 * Extended Ethernet port supported speeds and protocols.

drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c

+21 −0
Original line number Diff line number Diff line
@@ -1672,6 +1672,19 @@ mlxsw_sp2_mask_ethtool_400gaui_8[] = { 
#define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)



static const enum ethtool_link_mode_bit_indices

mlxsw_sp2_mask_ethtool_800gaui_8[] = {

	ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,

	ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT,

	ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT,

	ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,

	ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,

	ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT,

};



#define MLXSW_SP2_MASK_ETHTOOL_800GAUI_8_LEN \

	ARRAY_SIZE(mlxsw_sp2_mask_ethtool_800gaui_8)



#define MLXSW_SP_PORT_MASK_WIDTH_1X	BIT(0)

#define MLXSW_SP_PORT_MASK_WIDTH_2X	BIT(1)

#define MLXSW_SP_PORT_MASK_WIDTH_4X	BIT(2)
@@ -1820,6 +1833,14 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = { 
		.speed		= SPEED_400000,

		.width		= 8,

	},

	{

		.mask		= MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8,

		.mask_ethtool	= mlxsw_sp2_mask_ethtool_800gaui_8,

		.m_ethtool_len	= MLXSW_SP2_MASK_ETHTOOL_800GAUI_8_LEN,

		.mask_sup_width	= MLXSW_SP_PORT_MASK_WIDTH_8X,

		.speed		= SPEED_800000,

		.width		= 8,

	},

};



#define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)

drivers/net/phy/phy-core.c

+10 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
 */

const char *phy_speed_to_str(int speed)

{

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93,

	BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99,

		"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "

		"If a speed or mode has been added please update phy_speed_to_str "

		"and the PHY settings array.\n");
@@ -49,6 +49,8 @@ const char *phy_speed_to_str(int speed) 
		return "200Gbps";

	case SPEED_400000:

		return "400Gbps";

	case SPEED_800000:

		return "800Gbps";

	case SPEED_UNKNOWN:

		return "Unknown";

	default:
@@ -157,6 +159,13 @@ EXPORT_SYMBOL_GPL(phy_interface_num_ports); 
			       .bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}



static const struct phy_setting settings[] = {

	/* 800G */

	PHY_SETTING( 800000, FULL, 800000baseCR8_Full		),

	PHY_SETTING( 800000, FULL, 800000baseKR8_Full		),

	PHY_SETTING( 800000, FULL, 800000baseDR8_Full		),

	PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full		),

	PHY_SETTING( 800000, FULL, 800000baseSR8_Full		),

	PHY_SETTING( 800000, FULL, 800000baseVR8_Full		),

	/* 400G */

	PHY_SETTING( 400000, FULL, 400000baseCR8_Full		),

	PHY_SETTING( 400000, FULL, 400000baseKR8_Full		),

include/uapi/linux/ethtool.h

+8 −0
Original line number Diff line number Diff line
@@ -1737,6 +1737,13 @@ enum ethtool_link_mode_bit_indices { 
	ETHTOOL_LINK_MODE_100baseFX_Half_BIT		 = 90,

	ETHTOOL_LINK_MODE_100baseFX_Full_BIT		 = 91,

	ETHTOOL_LINK_MODE_10baseT1L_Full_BIT		 = 92,

	ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT	 = 93,

	ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT	 = 94,

	ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT	 = 95,

	ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT	 = 96,

	ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT	 = 97,

	ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT	 = 98,



	/* must be last entry */

	__ETHTOOL_LINK_MODE_MASK_NBITS

};
@@ -1848,6 +1855,7 @@ enum ethtool_link_mode_bit_indices { 
#define SPEED_100000		100000

#define SPEED_200000		200000

#define SPEED_400000		400000

#define SPEED_800000		800000



#define SPEED_UNKNOWN		-1