Commit ea41bd23 authored by chen gong's avatar chen gong Committed by Alex Deucher
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drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets for VGH 



For Vangogh:
The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation.
The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation.

Signed-off-by: default avatarchen gong <curry.gong@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b99a8c8f

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+16 −2
Original line number Diff line number Diff line
@@ -99,6 +99,10 @@ 
#define mmGCR_GENERAL_CNTL_Sienna_Cichlid			0x1580

#define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX	0



#define mmCGTS_TCC_DISABLE_Vangogh                0x5006

#define mmCGTS_TCC_DISABLE_Vangogh_BASE_IDX       1

#define mmCGTS_USER_TCC_DISABLE_Vangogh                0x5007

#define mmCGTS_USER_TCC_DISABLE_Vangogh_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025

#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1

#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
@@ -4936,8 +4940,18 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 
static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)

{

	/* TCCs are global (not instanced). */

	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |

	uint32_t tcc_disable;



	switch (adev->asic_type) {

	case CHIP_VANGOGH:

		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_Vangogh) |

				RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_Vangogh);

		break;

	default:

		tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |

				RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);

		break;

	}



	adev->gfx.config.tcc_disabled_mask =

		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |