Commit e9ff0226 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge tag 'devfreq-next-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux 

Pull devfreq updates for v5.13 from Chanwoo Choi:

"1. Update devfreq core

 - Register devfreq as a cooling device when adding devfreq device,
   basically if the flag of devfreq device is set as cooling device.

 - Add missing unlock opeation in devfreq_add_device

 - Use the next frequency as resume_freq instead of previous frequency
   when using opp-suspend property

 - Check whether .get_dev_status in struct devfreq_dev_profile is
   implemented or not by devfreq driver before calling .get_dev_status
   function.

 2. Update devfreq drivers

 - Use dev_err_probe to simplify the error handling on rk3399_dmc.c

 - Remove unused .get_dev_status function on imx8m-ddrc.c because
   imx8m_ddrc_get_dev_status has not returend the any current status
   of the device.

 - Remove unneeded of_match_ptr() from imx-bus.c and imx8m-ddrc.ca

 - Add missing phandle informatioon and replace undefined variable
   with integer value for rk3399_dmc.txt devicetree binding document.

 3. Fix minor issues

 - Fix the wrong set_freq path of userspace governor in
   drivers/devfreq/Kconfig.

 - Remove the invalid description from .get_target_freq in struct
   devfreq_dev_profile."

* tag 'devfreq-next-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux:
  PM / devfreq: imx8m-ddrc: Remove unneeded of_match_ptr()
  PM / devfreq: imx-bus: Remove unneeded of_match_ptr()
  PM / devfreq: imx8m-ddrc: Remove imx8m_ddrc_get_dev_status
  PM / devfreq: Remove the invalid description for get_target_freq
  PM / devfreq: Check get_dev_status in devfreq_update_stats
  PM / devfreq: Fix the wrong set_freq path for userspace governor in Kconfig
  dt-bindings: devfreq: rk3399_dmc: Remove references of unexistant defines
  dt-bindings: devfreq: rk3399_dmc: Add rockchip,pmu phandle.
  PM / devfreq: rk3399_dmc: Simplify with dev_err_probe()
  PM / devfreq: Use more accurate returned new_freq as resume_freq
  PM / devfreq: Unlock mutex and free devfreq struct in error path
  PM / devfreq: Register devfreq as a cooling device on demand
parents e49d033b 0a7dc831

Documentation/ABI/testing/sysfs-class-devfreq

+1 −4
Original line number Diff line number Diff line
@@ -97,10 +97,7 @@ Description: 
		object. The values are represented in ms. If the value is

		less than 1 jiffy, it is considered to be 0, which means

		no polling. This value is meaningless if the governor is

		not polling; thus. If the governor is not using

		devfreq-provided central polling

		(/sys/class/devfreq/.../central_polling is 0), this value

		may be useless.

		not polling.



		A list of governors that support the node:

		- simple_ondmenad

Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

+36 −39
Original line number Diff line number Diff line
@@ -12,6 +12,8 @@ Required properties: 
			 for details.

- center-supply:	 DMC supply node.

- status:		 Marks the node enabled/disabled.

- rockchip,pmu:		 Phandle to the syscon managing the "PMU general register

			 files".



Optional properties:

- interrupts:		 The CPU interrupt number. The interrupt specifier
@@ -77,24 +79,23 @@ Following properties relate to DDR timing: 


- rockchip,ddr3_drv :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is DDR3_DS_40ohm.

				  value is 40.



- rockchip,ddr3_odt :		  When the DRAM type is DDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is DDR3_ODT_120ohm.

				  is 120.



- rockchip,phy_ddr3_ca_drv :	  When the DRAM type is DDR3, this parameter defines

				  the phy side CA line (incluing command line,

				  address line and clock line) driver strength.

				  Default value is PHY_DRV_ODT_40.

				  Default value is 40.



- rockchip,phy_ddr3_dq_drv :	  When the DRAM type is DDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is PHY_DRV_ODT_40.

				  driver strength. Default value is 40.



- rockchip,phy_ddr3_odt : 	  When the DRAM type is DDR3, this parameter defines

				  the PHY side ODT strength. Default value is

				  PHY_DRV_ODT_240.

				  the PHY side ODT strength. Default value is 240.



- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines

				  then ODT disable frequency in MHz (Mega Hz).
@@ -104,25 +105,23 @@ Following properties relate to DDR timing: 


- rockchip,lpddr3_drv :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is LP3_DS_34ohm.

				  value is 34.



- rockchip,lpddr3_odt :		  When the DRAM type is LPDDR3, this parameter defines

				  the DRAM side ODT strength in ohms. Default value

				  is LP3_ODT_240ohm.

				  is 240.



- rockchip,phy_lpddr3_ca_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side CA line (including command line,

				  address line and clock line) driver strength.

				  Default value is PHY_DRV_ODT_40.

				  Default value is 40.



- rockchip,phy_lpddr3_dq_drv :	  When the DRAM type is LPDDR3, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is

				  PHY_DRV_ODT_40.

				  driver strength. Default value is 40.



- rockchip,phy_lpddr3_odt : 	  When dram type is LPDDR3, this parameter define

				  the phy side odt strength, default value is

				  PHY_DRV_ODT_240.

				  the phy side odt strength, default value is 240.



- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter

				  defines the ODT disable frequency in
@@ -132,32 +131,30 @@ Following properties relate to DDR timing: 


- rockchip,lpddr4_drv :		  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side driver strength in ohms. Default

				  value is LP4_PDDS_60ohm.

				  value is 60.



- rockchip,lpddr4_dq_odt : 	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on DQS/DQ line strength in ohms.

				  Default value is LP4_DQ_ODT_40ohm.

				  Default value is 40.



- rockchip,lpddr4_ca_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the DRAM side ODT on CA line strength in ohms.

				  Default value is LP4_CA_ODT_40ohm.

				  Default value is 40.



- rockchip,phy_lpddr4_ca_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side CA line (including command address

				  line) driver strength. Default value is

				  PHY_DRV_ODT_40.

				  line) driver strength. Default value is 40.



- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines

				  the PHY side clock line and CS line driver

				  strength. Default value is PHY_DRV_ODT_80.

				  strength. Default value is 80.



- rockchip,phy_lpddr4_dq_drv :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side DQ line (including DQS/DQ/DM line)

				  driver strength. Default value is PHY_DRV_ODT_80.

				  driver strength. Default value is 80.



- rockchip,phy_lpddr4_odt :	  When the DRAM type is LPDDR4, this parameter defines

				  the PHY side ODT strength. Default value is

				  PHY_DRV_ODT_60.

				  the PHY side ODT strength. Default value is 60.



Example:

	dmc_opp_table: dmc_opp_table {
@@ -193,23 +190,23 @@ Example: 
		rockchip,phy_dll_dis_freq = <125>;

		rockchip,auto_pd_dis_freq = <666>;

		rockchip,ddr3_odt_dis_freq = <333>;

		rockchip,ddr3_drv = <DDR3_DS_40ohm>;

		rockchip,ddr3_odt = <DDR3_ODT_120ohm>;

		rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;

		rockchip,ddr3_drv = <40>;

		rockchip,ddr3_odt = <120>;

		rockchip,phy_ddr3_ca_drv = <40>;

		rockchip,phy_ddr3_dq_drv = <40>;

		rockchip,phy_ddr3_odt = <240>;

		rockchip,lpddr3_odt_dis_freq = <333>;

		rockchip,lpddr3_drv = <LP3_DS_34ohm>;

		rockchip,lpddr3_odt = <LP3_ODT_240ohm>;

		rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;

		rockchip,lpddr3_drv = <34>;

		rockchip,lpddr3_odt = <240>;

		rockchip,phy_lpddr3_ca_drv = <40>;

		rockchip,phy_lpddr3_dq_drv = <40>;

		rockchip,phy_lpddr3_odt = <240>;

		rockchip,lpddr4_odt_dis_freq = <333>;

		rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;

		rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;

		rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;

		rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;

		rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;

		rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;

		rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;

		rockchip,lpddr4_drv = <60>;

		rockchip,lpddr4_dq_odt = <40>;

		rockchip,lpddr4_ca_odt = <40>;

		rockchip,phy_lpddr4_ca_drv = <40>;

		rockchip,phy_lpddr4_ck_cs_drv = <80>;

		rockchip,phy_lpddr4_dq_drv = <80>;

		rockchip,phy_lpddr4_odt = <60>;

	};

drivers/devfreq/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ config DEVFREQ_GOV_USERSPACE 
	help

	  Sets the frequency at the user specified one.

	  This governor returns the user configured frequency if there

	  has been an input to /sys/devices/.../power/devfreq_set_freq.

	  has been an input to /sys/devices/.../userspace/set_freq.

	  Otherwise, the governor does not change the frequency

	  given at the initialization.

drivers/devfreq/devfreq.c

+12 −2
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/kmod.h>

#include <linux/sched.h>

#include <linux/debugfs.h>

#include <linux/devfreq_cooling.h>

#include <linux/errno.h>

#include <linux/err.h>

#include <linux/init.h>
@@ -387,7 +388,7 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq, 
	devfreq->previous_freq = new_freq;



	if (devfreq->suspend_freq)

		devfreq->resume_freq = cur_freq;

		devfreq->resume_freq = new_freq;



	return err;

}
@@ -821,7 +822,8 @@ struct devfreq *devfreq_add_device(struct device *dev, 


	if (devfreq->profile->timer < 0

		|| devfreq->profile->timer >= DEVFREQ_TIMER_NUM) {

		goto err_out;

		mutex_unlock(&devfreq->lock);

		goto err_dev;

	}



	if (!devfreq->profile->max_state && !devfreq->profile->freq_table) {
@@ -935,6 +937,12 @@ struct devfreq *devfreq_add_device(struct device *dev, 


	mutex_unlock(&devfreq_list_lock);



	if (devfreq->profile->is_cooling_device) {

		devfreq->cdev = devfreq_cooling_em_register(devfreq, NULL);

		if (IS_ERR(devfreq->cdev))

			devfreq->cdev = NULL;

	}



	return devfreq;



err_init:
@@ -960,6 +968,8 @@ int devfreq_remove_device(struct devfreq *devfreq) 
	if (!devfreq)

		return -EINVAL;



	devfreq_cooling_unregister(devfreq->cdev);



	if (devfreq->governor) {

		devfreq->governor->event_handler(devfreq,

						 DEVFREQ_GOV_STOP, NULL);

drivers/devfreq/governor.h

+3 −2
Original line number Diff line number Diff line
@@ -57,8 +57,6 @@ 
 *			Basically, get_target_freq will run

 *			devfreq_dev_profile.get_dev_status() to get the

 *			status of the device (load = busy_time / total_time).

 *			If no_central_polling is set, this callback is called

 *			only with update_devfreq() notified by OPP.

 * @event_handler:      Callback for devfreq core framework to notify events

 *                      to governors. Events include per device governor

 *                      init and exit, opp changes out of devfreq, suspend
@@ -91,6 +89,9 @@ int devfreq_update_target(struct devfreq *devfreq, unsigned long freq); 


static inline int devfreq_update_stats(struct devfreq *df)

{

	if (!df->profile->get_dev_status)

		return -EINVAL;



	return df->profile->get_dev_status(df->dev.parent, &df->last_status);

}

#endif /* _GOVERNOR_H */