Commit e9f9bcd5 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Use parameterized GPR register definitions everywhere 



Since we have an engine-parameterized macro GEN8_RING_CS_GPR, let's use
that in place of the HSW_CS_GPR and BCS_GPR register definitions.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220111051600.3429104-2-matthew.d.roper@intel.com
parent 583998c5

drivers/gpu/drm/i915/i915_cmd_parser.c

+36 −32
Original line number Diff line number Diff line
@@ -592,6 +592,10 @@ struct drm_i915_reg_descriptor { 
	{ .addr = _reg(idx) }, \

	{ .addr = _reg ## _UDW(idx) }



#define REG64_BASE_IDX(_reg, base, idx) \

	{ .addr = _reg(base, idx) }, \

	{ .addr = _reg ## _UDW(base, idx) }



static const struct drm_i915_reg_descriptor gen7_render_regs[] = {

	REG64(GPGPU_THREADS_DISPATCHED),

	REG64(HS_INVOCATION_COUNT),
@@ -637,22 +641,22 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { 
};



static const struct drm_i915_reg_descriptor hsw_render_regs[] = {

	REG64_IDX(HSW_CS_GPR, 0),

	REG64_IDX(HSW_CS_GPR, 1),

	REG64_IDX(HSW_CS_GPR, 2),

	REG64_IDX(HSW_CS_GPR, 3),

	REG64_IDX(HSW_CS_GPR, 4),

	REG64_IDX(HSW_CS_GPR, 5),

	REG64_IDX(HSW_CS_GPR, 6),

	REG64_IDX(HSW_CS_GPR, 7),

	REG64_IDX(HSW_CS_GPR, 8),

	REG64_IDX(HSW_CS_GPR, 9),

	REG64_IDX(HSW_CS_GPR, 10),

	REG64_IDX(HSW_CS_GPR, 11),

	REG64_IDX(HSW_CS_GPR, 12),

	REG64_IDX(HSW_CS_GPR, 13),

	REG64_IDX(HSW_CS_GPR, 14),

	REG64_IDX(HSW_CS_GPR, 15),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 0),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 1),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 2),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 3),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 4),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 5),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 6),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 7),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 8),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 9),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 10),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 11),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 12),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 13),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 14),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, RENDER_RING_BASE, 15),

	REG32(HSW_SCRATCH1,

	      .mask = ~HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE,

	      .value = 0),
@@ -675,22 +679,22 @@ static const struct drm_i915_reg_descriptor gen9_blt_regs[] = { 
	REG32(BCS_SWCTRL),

	REG64_IDX(RING_TIMESTAMP, BLT_RING_BASE),

	REG32_IDX(RING_CTX_TIMESTAMP, BLT_RING_BASE),

	REG64_IDX(BCS_GPR, 0),

	REG64_IDX(BCS_GPR, 1),

	REG64_IDX(BCS_GPR, 2),

	REG64_IDX(BCS_GPR, 3),

	REG64_IDX(BCS_GPR, 4),

	REG64_IDX(BCS_GPR, 5),

	REG64_IDX(BCS_GPR, 6),

	REG64_IDX(BCS_GPR, 7),

	REG64_IDX(BCS_GPR, 8),

	REG64_IDX(BCS_GPR, 9),

	REG64_IDX(BCS_GPR, 10),

	REG64_IDX(BCS_GPR, 11),

	REG64_IDX(BCS_GPR, 12),

	REG64_IDX(BCS_GPR, 13),

	REG64_IDX(BCS_GPR, 14),

	REG64_IDX(BCS_GPR, 15),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 0),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 1),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 2),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 3),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 4),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 5),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 6),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 7),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 8),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 9),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 10),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 11),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 12),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 13),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 14),

	REG64_BASE_IDX(GEN8_RING_CS_GPR, BLT_RING_BASE, 15),

};



#undef REG64

drivers/gpu/drm/i915/i915_reg.h

+0 −8
Original line number Diff line number Diff line
@@ -509,10 +509,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   BCS_SRC_Y REG_BIT(0)

#define   BCS_DST_Y REG_BIT(1)



/* There are 16 GPR registers */

#define BCS_GPR(n)	_MMIO(0x22600 + (n) * 8)

#define BCS_GPR_UDW(n)	_MMIO(0x22600 + (n) * 8 + 4)



#define GPGPU_THREADS_DISPATCHED        _MMIO(0x2290)

#define GPGPU_THREADS_DISPATCHED_UDW	_MMIO(0x2290 + 4)

#define HS_INVOCATION_COUNT             _MMIO(0x2300)
@@ -556,10 +552,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define GEN7_GPGPU_DISPATCHDIMY         _MMIO(0x2504)

#define GEN7_GPGPU_DISPATCHDIMZ         _MMIO(0x2508)



/* There are the 16 64-bit CS General Purpose Registers */

#define HSW_CS_GPR(n)                   _MMIO(0x2600 + (n) * 8)

#define HSW_CS_GPR_UDW(n)               _MMIO(0x2600 + (n) * 8 + 4)



#define GEN7_OACONTROL _MMIO(0x2360)

#define  GEN7_OACONTROL_CTX_MASK	    0xFFFFF000

#define  GEN7_OACONTROL_TIMER_PERIOD_MASK   0x3F