Commit e9d9ce54 authored by Marijn Suijten's avatar Marijn Suijten Committed by Abhinav Kumar
Browse files

drm/msm/dpu: Move non-MDP_TOP INTF_INTR offsets out of hwio header 



These offsets do not fall under the MDP TOP block and do not fit the
comment right above.  Move them to dpu_hw_interrupts.c next to the
repsective MDP_INTF_x_OFF interrupt block offsets.

Fixes: 25fdd593 ("drm/msm: Add SDM845 DPU support")
Signed-off-by: default avatarMarijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/534203/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-3-27ce1a5ab5c6@somainline.org


Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
parent cfbc21d1

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

+4 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ 


/*

 * Register offsets in MDSS register file for the interrupt registers

 * w.r.t. to the MDP base

 * w.r.t. the MDP base

 */

#define MDP_SSPP_TOP0_OFF		0x0

#define MDP_INTF_0_OFF			0x6A000
@@ -24,6 +24,9 @@ 
#define MDP_INTF_3_OFF			0x6B800

#define MDP_INTF_4_OFF			0x6C000

#define MDP_INTF_5_OFF			0x6C800

#define INTF_INTR_EN			0x1c0

#define INTF_INTR_STATUS		0x1c4

#define INTF_INTR_CLEAR			0x1c8

#define MDP_AD4_0_OFF			0x7C000

#define MDP_AD4_1_OFF			0x7D000

#define MDP_AD4_INTR_EN_OFF		0x41c

drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h

+0 −3
Original line number Diff line number Diff line
@@ -21,9 +21,6 @@ 
#define HIST_INTR_EN                    0x01c

#define HIST_INTR_STATUS                0x020

#define HIST_INTR_CLEAR                 0x024

#define INTF_INTR_EN                    0x1C0

#define INTF_INTR_STATUS                0x1C4

#define INTF_INTR_CLEAR                 0x1C8

#define SPLIT_DISPLAY_EN                0x2F4

#define SPLIT_DISPLAY_UPPER_PIPE_CTRL   0x2F8

#define DSPP_IGC_COLOR0_RAM_LUTN        0x300