Commit e9cfe00b authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Fix updating infoframe for DCN3.1 eDP 



[Why]
We're only treating TMDS as a valid target for infoframe updates which
results in PSR being unable to transition from state 4 to state 5.

[How]
Also allow infoframe updates for DCN3.1 - following how we handle
this path for earlier ASIC as well.

Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 43a44c53

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -390,7 +390,7 @@ void dcn31_update_info_frame(struct pipe_ctx *pipe_ctx) 
	is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);

	is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);



	if (!is_hdmi_tmds)

	if (!is_hdmi_tmds && !is_dp)

		return;



	if (is_hdmi_tmds)