Commit e981deb1 authored by Kunkun Jiang's avatar Kunkun Jiang Committed by Dongxu Sun
Browse files

mbigen: vtimer: add support for MBIX1_CPPI_NEGEDGE_CLR_EN_SETR(CLRR) 

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8URKX


CVE: NA

------------------------------------------------------------------

Disable gic_auto_clr when vcpu put and enable it when vcpu load.

Signed-off-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Signed-off-by: default avatarKunkun Jiang <jiangkunkun@huawei.com>
Signed-off-by: default avatarDongxu Sun <sundongxu3@huawei.com>
parent 747c4475

arch/arm64/kvm/arch_timer.c

+14 −2
Original line number Diff line number Diff line
@@ -676,6 +676,13 @@ static void kvm_vtimer_mbigen_auto_clr_set(struct kvm_vcpu *vcpu, bool set) 
	vtimer_mbigen_set_auto_clr(vcpu->cpu, set);

}



static void kvm_vtimer_gic_auto_clr_set(struct kvm_vcpu *vcpu, bool set)

{

	BUG_ON(!vtimer_is_irqbypass());



	vtimer_gic_set_auto_clr(vcpu->cpu, set);

}



static void kvm_vtimer_mbigen_restore_stat(struct kvm_vcpu *vcpu)

{

	struct vtimer_mbigen_context *mbigen_ctx = vcpu_vtimer_mbigen(vcpu);
@@ -912,8 +919,10 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) 
	timer_restore_state(map.direct_vtimer);



#ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS

	if (vtimer_is_irqbypass())

	if (vtimer_is_irqbypass()) {

		kvm_vtimer_mbigen_auto_clr_set(vcpu, true);

		kvm_vtimer_gic_auto_clr_set(vcpu, true);

	}

#endif

	if (map.direct_ptimer)

		timer_restore_state(map.direct_ptimer);
@@ -978,9 +987,12 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) 
	get_timer_map(vcpu, &map);



#ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS

	if (vtimer_is_irqbypass())

	if (vtimer_is_irqbypass()) {

		kvm_vtimer_mbigen_auto_clr_set(vcpu, false);

		kvm_vtimer_gic_auto_clr_set(vcpu, false);

	}

#endif



	timer_save_state(map.direct_vtimer);



#ifdef CONFIG_VIRT_VTIMER_IRQ_BYPASS

drivers/irqchip/irq-mbigen.c

+25 −0
Original line number Diff line number Diff line
@@ -89,6 +89,8 @@ 
#define VTIMER_MBIGEN_REG_SET_AUTO_CLR_OFFSET  0x1100

#define VTIMER_MBIGEN_REG_CLR_AUTO_CLR_OFFSET  0x1110

#define VTIMER_MBIGEN_REG_ATV_STAT_OFFSET      0x1120

#define VTIMER_GIC_REG_SET_AUTO_CLR_OFFSET     0x1150

#define VTIMER_GIC_REG_CLR_AUTO_CLR_OFFSET     0x1160

#define VTIMER_MBIGEN_REG_VEC_OFFSET           0x1200

#define VTIMER_MBIGEN_REG_ATV_CLR_OFFSET       0xa008
@@ -225,6 +227,29 @@ void vtimer_mbigen_set_auto_clr(int cpu_id, bool set) 
	dsb(sy);

}



void vtimer_gic_set_auto_clr(int cpu_id, bool set)

{

	struct vtimer_mbigen_device *chip;

	void __iomem *addr;

	int cpu_abs_offset;

	u64 offset;

	u32 val;



	chip = get_vtimer_mbigen(cpu_id);

	if (!chip)

		return;



	cpu_abs_offset = get_abs_offset(cpu_id, chip->cpu_base);

	offset = set ? VTIMER_GIC_REG_SET_AUTO_CLR_OFFSET :

		 VTIMER_GIC_REG_CLR_AUTO_CLR_OFFSET;

	addr = chip->base + offset +

	       (cpu_abs_offset / PPIS_PER_MBIGEN_NODE) * VTIMER_MBIGEN_REG_WIDTH;

	val = 1 << (cpu_abs_offset % PPIS_PER_MBIGEN_NODE);



	writel_relaxed(val, addr);

	dsb(sy);

}



void vtimer_mbigen_set_active(int cpu_id, bool set)

{

	struct vtimer_mbigen_device *chip;

include/clocksource/arm_arch_timer.h

+1 −0
Original line number Diff line number Diff line
@@ -124,6 +124,7 @@ static inline bool vtimer_irqbypass_hw_support(struct arch_timer_kvm_info *info) 
void vtimer_mbigen_set_vector(int cpu_id, u16 vpeid);

bool vtimer_mbigen_get_active(int cpu_id);

void vtimer_mbigen_set_auto_clr(int cpu_id, bool set);

void vtimer_gic_set_auto_clr(int cpu_id, bool set);

void vtimer_mbigen_set_active(int cpu_id, bool set);

#endif