Unverified Commit e95a0071 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!6256 [OLK-6.6] bugfix from upstream v6.9 for AMD EPYC perf 

Merge Pull Request from: @kile2009 
 
598c2fafc06fe5c56a1a415fb7b544b31453d637 v6.9-rc2 perf/x86/amd/lbr: Use freeze based on availability
c7b2edd8377be983442c1344cb940cd2ac21b601 v6.9-rc2 perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later
68cdf1e6e8f2ce78ed7d8f5d80844fd75a9c54ff v6.9-rc2 perf/x86/amd/core: Define a proper ref-cycles event for Zen 4 and later

perf:
https://lore.kernel.org/all/cover.1711352180.git.sandipan.das@amd.com/
https://lore.kernel.org/all/69a453c97cfd11c6f2584b19f937fe6df741510f.1711091584.git.sandipan.das@amd.com/#r 
 
Link:https://gitee.com/openeuler/kernel/pulls/6256

 

Reviewed-by: default avatarWei Li <liwei391@huawei.com>
Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Signed-off-by: default avatarXie XiuQi <xiexiuqi@huawei.com>
parents 47274528 820fd03e

arch/x86/events/amd/core.c

+34 −5
Original line number Diff line number Diff line
@@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = 
/*

 * AMD Performance Monitor Family 17h and later:

 */

static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =

static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
@@ -262,10 +262,39 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = 
	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= 0x0187,

};



static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,

	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,

	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,

};



static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =

{

	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,

	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,

	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,

	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,

	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,

	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,

	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,

	[PERF_COUNT_HW_REF_CPU_CYCLES]		= 0x100000120,

};



static u64 amd_pmu_event_map(int hw_event)

{

	if (boot_cpu_data.x86 >= 0x17)

		return amd_f17h_perfmon_event_map[hw_event];

	if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)

		return amd_zen4_perfmon_event_map[hw_event];



	if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)

		return amd_zen2_perfmon_event_map[hw_event];



	if (cpu_feature_enabled(X86_FEATURE_ZEN1))

		return amd_zen1_perfmon_event_map[hw_event];



	return amd_perfmon_event_map[hw_event];

}
@@ -904,8 +933,8 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) 
	if (!status)

		goto done;



	/* Read branch records before unfreezing */

	if (status & GLOBAL_STATUS_LBRS_FROZEN) {

	/* Read branch records */

	if (x86_pmu.lbr_nr) {

		amd_pmu_lbr_read();

		status &= ~GLOBAL_STATUS_LBRS_FROZEN;

	}

arch/x86/events/amd/lbr.c

+10 −6
Original line number Diff line number Diff line
@@ -402,10 +402,12 @@ void amd_pmu_lbr_enable_all(void) 
		wrmsrl(MSR_AMD64_LBR_SELECT, lbr_select);

	}



	if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {

		rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);

	rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);



		wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);

	}



	rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);

	wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg | DBG_EXTN_CFG_LBRV2EN);

}
@@ -418,11 +420,13 @@ void amd_pmu_lbr_disable_all(void) 
		return;



	rdmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg);

	rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);



	wrmsrl(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN);



	if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) {

		rdmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl);

		wrmsrl(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI);

	}

}



__init int amd_pmu_lbr_init(void)

{

arch/x86/include/asm/cpufeatures.h

+8 −0
Original line number Diff line number Diff line
@@ -475,6 +475,14 @@ 
#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */

#define X86_FEATURE_SRSO_NO		(20*32+29) /* "" CPU is not affected by SRSO */



/*

 * Extended auxiliary flags: Linux defined - for features scattered in various

 * CPUID levels like 0x80000022, etc.

 *

 * Reuse free bits when adding new feature flags!

 */

#define X86_FEATURE_AMD_LBR_PMC_FREEZE	(21*32+ 0) /* AMD LBR and PMC Freeze */



/*

 * BUG word(s)

 */

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_BMEC,		CPUID_EBX,  3, 0x80000020, 0 },

	{ X86_FEATURE_PERFMON_V2,	CPUID_EAX,  0, 0x80000022, 0 },

	{ X86_FEATURE_AMD_LBR_V2,	CPUID_EAX,  1, 0x80000022, 0 },

	{ X86_FEATURE_AMD_LBR_PMC_FREEZE,	CPUID_EAX,  2, 0x80000022, 0 },

	{ 0, 0, 0, 0, 0 }

};