Commit e957ca2a authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Stephen Boyd
Browse files

clk: qcom: gcc-sc7180: use ARRAY_SIZE instead of specifying num_parents 



Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-30-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent b7072913

drivers/clk/qcom/gcc-sc7180.c

+16 −16
Original line number Diff line number Diff line
@@ -285,7 +285,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_cpuss_ahb_clk_src",

		.parent_data = gcc_parent_data_0_ao,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0_ao),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_ops,

		},
@@ -309,7 +309,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_gp1_clk_src",

		.parent_data = gcc_parent_data_4,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parent_data_4),

		.ops = &clk_rcg2_ops,

	},

};
@@ -323,7 +323,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_gp2_clk_src",

		.parent_data = gcc_parent_data_4,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parent_data_4),

		.ops = &clk_rcg2_ops,

	},

};
@@ -337,7 +337,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_gp3_clk_src",

		.parent_data = gcc_parent_data_4,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parent_data_4),

		.ops = &clk_rcg2_ops,

	},

};
@@ -357,7 +357,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_pdm2_clk_src",

		.parent_data = gcc_parent_data_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.ops = &clk_rcg2_ops,

	},

};
@@ -378,7 +378,7 @@ static struct clk_rcg2 gcc_qspi_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_qspi_core_clk_src",

		.parent_data = gcc_parent_data_2,

		.num_parents = 6,

		.num_parents = ARRAY_SIZE(gcc_parent_data_2),

		.ops = &clk_rcg2_ops,

	},

};
@@ -619,7 +619,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc1_apps_clk_src",

		.parent_data = gcc_parent_data_1,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parent_data_1),

		.ops = &clk_rcg2_floor_ops,

	},

};
@@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc1_ice_core_clk_src",

		.parent_data = gcc_parent_data_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.ops = &clk_rcg2_ops,

	},

};
@@ -666,7 +666,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_sdcc2_apps_clk_src",

		.parent_data = gcc_parent_data_5,

		.num_parents = 5,

		.num_parents = ARRAY_SIZE(gcc_parent_data_5),

		.ops = &clk_rcg2_floor_ops,

	},

};
@@ -689,7 +689,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_axi_clk_src",

		.parent_data = gcc_parent_data_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.ops = &clk_rcg2_ops,

	},

};
@@ -711,7 +711,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_ice_core_clk_src",

		.parent_data = gcc_parent_data_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.ops = &clk_rcg2_ops,

	},

};
@@ -731,7 +731,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_phy_aux_clk_src",

		.parent_data = gcc_parent_data_3,

		.num_parents = 3,

		.num_parents = ARRAY_SIZE(gcc_parent_data_3),

		.ops = &clk_rcg2_ops,

	},

};
@@ -752,7 +752,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_ufs_phy_unipro_core_clk_src",

		.parent_data = gcc_parent_data_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.ops = &clk_rcg2_ops,

	},

};
@@ -774,7 +774,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb30_prim_master_clk_src",

		.parent_data = gcc_parent_data_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.ops = &clk_rcg2_ops,

	},

};
@@ -794,7 +794,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb30_prim_mock_utmi_clk_src",

		.parent_data = gcc_parent_data_0,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.ops = &clk_rcg2_ops,

	},

};
@@ -813,7 +813,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { 
	.clkr.hw.init = &(struct clk_init_data){

		.name = "gcc_usb3_prim_phy_aux_clk_src",

		.parent_data = gcc_parent_data_6,

		.num_parents = 4,

		.num_parents = ARRAY_SIZE(gcc_parent_data_6),

		.ops = &clk_rcg2_ops,

	},

};