Unverified Commit e9210500 authored by Sergey Matyukevich's avatar Sergey Matyukevich Committed by Palmer Dabbelt
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Revert "riscv: mm: notify remote harts about mmu cache updates" 



This reverts the remaining bits of commit 4bd1d80e ("riscv: mm:
notify remote harts harts about mmu cache updates").

According to bug reports, suggested approach to fix stale TLB entries
is not sufficient. It needs to be replaced by a more robust solution.

Fixes: 4bd1d80e ("riscv: mm: notify remote harts about mmu cache updates")
Reported-by: default avatarZong Li <zong.li@sifive.com>
Reported-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: default avatarSergey Matyukevich <sergey.matyukevich@syntacore.com>
Cc: stable@vger.kernel.org
Reviewed-by: default avatarGuo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230226150137.1919750-2-geomatsi@gmail.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 1b929c02

arch/riscv/include/asm/mmu.h

+0 −2
Original line number Diff line number Diff line
@@ -19,8 +19,6 @@ typedef struct { 
#ifdef CONFIG_SMP

	/* A local icache flush is needed before user execution can resume. */

	cpumask_t icache_stale_mask;

	/* A local tlb flush is needed before user execution can resume. */

	cpumask_t tlb_stale_mask;

#endif

} mm_context_t;

arch/riscv/include/asm/tlbflush.h

+0 −18
Original line number Diff line number Diff line
@@ -22,24 +22,6 @@ static inline void local_flush_tlb_page(unsigned long addr) 
{

	ALT_FLUSH_TLB_PAGE(__asm__ __volatile__ ("sfence.vma %0" : : "r" (addr) : "memory"));

}



static inline void local_flush_tlb_all_asid(unsigned long asid)

{

	__asm__ __volatile__ ("sfence.vma x0, %0"

			:

			: "r" (asid)

			: "memory");

}



static inline void local_flush_tlb_page_asid(unsigned long addr,

		unsigned long asid)

{

	__asm__ __volatile__ ("sfence.vma %0, %1"

			:

			: "r" (addr), "r" (asid)

			: "memory");

}



#else /* CONFIG_MMU */

#define local_flush_tlb_all()			do { } while (0)

#define local_flush_tlb_page(addr)		do { } while (0)

arch/riscv/mm/context.c

+0 −10
Original line number Diff line number Diff line
@@ -196,16 +196,6 @@ static void set_mm_asid(struct mm_struct *mm, unsigned int cpu) 


	if (need_flush_tlb)

		local_flush_tlb_all();

#ifdef CONFIG_SMP

	else {

		cpumask_t *mask = &mm->context.tlb_stale_mask;



		if (cpumask_test_cpu(cpu, mask)) {

			cpumask_clear_cpu(cpu, mask);

			local_flush_tlb_all_asid(cntx & asid_mask);

		}

	}

#endif

}



static void set_mm_noasid(struct mm_struct *mm)

arch/riscv/mm/tlbflush.c

+17 −11
Original line number Diff line number Diff line
@@ -5,7 +5,23 @@ 
#include <linux/sched.h>

#include <asm/sbi.h>

#include <asm/mmu_context.h>

#include <asm/tlbflush.h>



static inline void local_flush_tlb_all_asid(unsigned long asid)

{

	__asm__ __volatile__ ("sfence.vma x0, %0"

			:

			: "r" (asid)

			: "memory");

}



static inline void local_flush_tlb_page_asid(unsigned long addr,

		unsigned long asid)

{

	__asm__ __volatile__ ("sfence.vma %0, %1"

			:

			: "r" (addr), "r" (asid)

			: "memory");

}



void flush_tlb_all(void)

{
@@ -15,7 +31,6 @@ void flush_tlb_all(void) 
static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start,

				  unsigned long size, unsigned long stride)

{

	struct cpumask *pmask = &mm->context.tlb_stale_mask;

	struct cpumask *cmask = mm_cpumask(mm);

	unsigned int cpuid;

	bool broadcast;
@@ -29,15 +44,6 @@ static void __sbi_tlb_flush_range(struct mm_struct *mm, unsigned long start, 
	if (static_branch_unlikely(&use_asid_allocator)) {

		unsigned long asid = atomic_long_read(&mm->context.id);



		/*

		 * TLB will be immediately flushed on harts concurrently

		 * executing this MM context. TLB flush on other harts

		 * is deferred until this MM context migrates there.

		 */

		cpumask_setall(pmask);

		cpumask_clear_cpu(cpuid, pmask);

		cpumask_andnot(pmask, pmask, cmask);



		if (broadcast) {

			sbi_remote_sfence_vma_asid(cmask, start, size, asid);

		} else if (size <= stride) {