Commit e8df8511 authored by Juan Zhou's avatar Juan Zhou
Browse files

Revert "RDMA/hns: Remove VF extend configuration" 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8E9OJ



--------------------------------------------------------------------------

This reverts commit f4fe3c91.

Signed-off-by: default avatarJuan Zhou <zhoujuan51@h-partners.com>
parent c647f880

drivers/infiniband/hw/hns/hns_roce_device.h

+1 −0
Original line number Diff line number Diff line
@@ -840,6 +840,7 @@ struct hns_roce_caps { 
	u32		max_rq_sg;

	u32		rsv0;

	u32		num_qps;

	u32		num_pi_qps;

	u32		reserved_qps;

	u32		num_srqs;

	u32		max_wqes;

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+74 −10
Original line number Diff line number Diff line
@@ -1950,6 +1950,29 @@ static int load_func_res_caps(struct hns_roce_dev *hr_dev, bool is_vf) 
	return 0;

}



static int load_ext_cfg_caps(struct hns_roce_dev *hr_dev, bool is_vf)

{

	struct hns_roce_cmq_desc desc;

	struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;

	struct hns_roce_caps *caps = &hr_dev->caps;

	u32 func_num, qp_num;

	int ret;



	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, true);

	ret = hns_roce_cmq_send(hr_dev, &desc, 1);

	if (ret)

		return ret;



	func_num = is_vf ? 1 : max_t(u32, 1, hr_dev->func_num);

	qp_num = hr_reg_read(req, EXT_CFG_QP_PI_NUM) / func_num;

	caps->num_pi_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);



	qp_num = hr_reg_read(req, EXT_CFG_QP_NUM) / func_num;

	caps->num_qps = round_down(qp_num, HNS_ROCE_QP_BANK_NUM);



	return 0;

}



static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev)

{

	struct hns_roce_cmq_desc desc;
@@ -1970,37 +1993,50 @@ static int load_pf_timer_res_caps(struct hns_roce_dev *hr_dev) 
	return 0;

}



static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)

static int query_func_resource_caps(struct hns_roce_dev *hr_dev, bool is_vf)

{

	struct device *dev = hr_dev->dev;

	int ret;



	ret = load_func_res_caps(hr_dev, false);

	ret = load_func_res_caps(hr_dev, is_vf);

	if (ret) {

		dev_err(dev, "failed to load pf res caps, ret = %d.\n", ret);

		dev_err(dev, "failed to load res caps, ret = %d (%s).\n", ret,

			is_vf ? "vf" : "pf");

		return ret;

	}



	ret = load_pf_timer_res_caps(hr_dev);

	if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {

		ret = load_ext_cfg_caps(hr_dev, is_vf);

		if (ret)

		dev_err(dev, "failed to load pf timer resource, ret = %d.\n",

			ret);

			dev_err(dev, "failed to load ext cfg, ret = %d (%s).\n",

				ret, is_vf ? "vf" : "pf");

	}



	return ret;

}



static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)

static int hns_roce_query_pf_resource(struct hns_roce_dev *hr_dev)

{

	struct device *dev = hr_dev->dev;

	int ret;



	ret = load_func_res_caps(hr_dev, true);

	ret = query_func_resource_caps(hr_dev, false);

	if (ret)

		return ret;



	ret = load_pf_timer_res_caps(hr_dev);

	if (ret)

		dev_err(dev, "failed to load vf res caps, ret = %d.\n", ret);

		dev_err(dev, "failed to load pf timer resource, ret = %d.\n",

			ret);



	return ret;

}



static int hns_roce_query_vf_resource(struct hns_roce_dev *hr_dev)

{

	return query_func_resource_caps(hr_dev, true);

}



static int __hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev,

					  u32 vf_id)

{
@@ -2083,6 +2119,24 @@ static int config_vf_hem_resource(struct hns_roce_dev *hr_dev, int vf_id) 
	return hns_roce_cmq_send(hr_dev, desc, 2);

}



static int config_vf_ext_resource(struct hns_roce_dev *hr_dev, u32 vf_id)

{

	struct hns_roce_cmq_desc desc;

	struct hns_roce_cmq_req *req = (struct hns_roce_cmq_req *)desc.data;

	struct hns_roce_caps *caps = &hr_dev->caps;



	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_EXT_CFG, false);



	hr_reg_write(req, EXT_CFG_VF_ID, vf_id);



	hr_reg_write(req, EXT_CFG_QP_PI_NUM, caps->num_pi_qps);

	hr_reg_write(req, EXT_CFG_QP_PI_IDX, vf_id * caps->num_pi_qps);

	hr_reg_write(req, EXT_CFG_QP_NUM, caps->num_qps);

	hr_reg_write(req, EXT_CFG_QP_IDX, vf_id * caps->num_qps);



	return hns_roce_cmq_send(hr_dev, &desc, 1);

}



static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev)

{

	u32 func_num = max_t(u32, 1, hr_dev->func_num);
@@ -2097,6 +2151,16 @@ static int hns_roce_alloc_vf_resource(struct hns_roce_dev *hr_dev) 
				vf_id, ret);

			return ret;

		}



		if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {

			ret = config_vf_ext_resource(hr_dev, vf_id);

			if (ret) {

				dev_err(hr_dev->dev,

					"failed to config vf-%u ext res, ret = %d.\n",

					vf_id, ret);

				return ret;

			}

		}

	}



	return 0;

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+10 −0
Original line number Diff line number Diff line
@@ -229,6 +229,7 @@ enum hns_roce_opcode_type { 
	HNS_ROCE_OPC_CFG_GMV_TBL			= 0x850f,

	HNS_ROCE_OPC_CFG_GMV_BT				= 0x8510,

	HNS_ROCE_OPC_SYNC_MB				= 0x8511,

	HNS_ROCE_OPC_EXT_CFG				= 0x8512,

	HNS_ROCE_QUERY_RAM_ECC				= 0x8513,

	HNS_SWITCH_PARAMETER_CFG			= 0x1033,

	HNS_ROCE_OPC_SET_BOND_INFO			= 0x8601,
@@ -1011,6 +1012,15 @@ struct hns_roce_func_clear { 
#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_INTERVAL	40

#define HNS_ROCE_V2_READ_FUNC_CLEAR_FLAG_FAIL_WAIT	20



/* Fields of HNS_ROCE_OPC_EXT_CFG */

#define EXT_CFG_VF_ID CMQ_REQ_FIELD_LOC(31, 0)

#define EXT_CFG_QP_PI_IDX CMQ_REQ_FIELD_LOC(45, 32)

#define EXT_CFG_QP_PI_NUM CMQ_REQ_FIELD_LOC(63, 48)

#define EXT_CFG_QP_NUM CMQ_REQ_FIELD_LOC(87, 64)

#define EXT_CFG_QP_IDX CMQ_REQ_FIELD_LOC(119, 96)

#define EXT_CFG_LLM_IDX CMQ_REQ_FIELD_LOC(139, 128)

#define EXT_CFG_LLM_NUM CMQ_REQ_FIELD_LOC(156, 144)



#define CFG_LLM_A_BA_L CMQ_REQ_FIELD_LOC(31, 0)

#define CFG_LLM_A_BA_H CMQ_REQ_FIELD_LOC(63, 32)

#define CFG_LLM_A_DEPTH CMQ_REQ_FIELD_LOC(76, 64)