Commit e8c047b4 authored by Hector Palacios's avatar Hector Palacios Committed by Miquel Raynal
Browse files

mtd: rawnand: hynix: fix up bit 0 of sdr_timing_mode 



According to the ONFI specification, bit 0 of 'SDR timing mode support'
(bytes 129-130) "shall be 1". That means the NAND supports at least
timing mode 0.

NAND chip Hynix H27U4G8F2GDA-BI (at least) is reading a 0 on this field
which makes nand_choose_best_sdr_timings() return with error and the
probe function to eventually fail.

Given that sdr_timing_modes bit 0 must be 1 by specification, force
it in case the NAND reports it is not set. This is a safe assumption
because the mode 0 is the minimum (safer) set of timings that the
NAND can work with.

Signed-off-by: default avatarHector Palacios <hector.palacios@digi.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230223165104.525852-1-hector.palacios@digi.com
Link: https://lore.kernel.org/linux-mtd/20230310080609.1930869-1-hector.palacios@digi.com
parent 4080d536

drivers/mtd/nand/raw/nand_hynix.c

+13 −0
Original line number Diff line number Diff line
@@ -728,8 +728,21 @@ static int hynix_nand_init(struct nand_chip *chip) 
	return ret;

}



static void hynix_fixup_onfi_param_page(struct nand_chip *chip,

					struct nand_onfi_params *p)

{

	/*

	 * Certain chips might report a 0 on sdr_timing_mode field

	 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI.

	 * According to ONFI specification, bit 0 of this field "shall be 1".

	 * Forcibly set this bit.

	 */

	p->sdr_timing_modes |= cpu_to_le16(BIT(0));

}



const struct nand_manufacturer_ops hynix_nand_manuf_ops = {

	.detect = hynix_nand_decode_id,

	.init = hynix_nand_init,

	.cleanup = hynix_nand_cleanup,

	.fixup_onfi_param_page = hynix_fixup_onfi_param_page,

};