Unverified Commit e8bcacda authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'juno-updates-5.19' of... 

Merge tag 'juno-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt

Arm FVP/Juno device tree updates for v5.19

The main and bulk of the change is the addition of new platform
Arm corstone1000(both FVP and FPGA versions). Also, there are
addition of Coresight Cross Trigger Interface(CTI) support on Juno,
fix for incorrect SCMI power domain IDs, addition of virtio-rng
on FVP which is default disabled as it works only on latest versions
of the FVP model.

Other miscellanous changes include dropping of useless
'dma-channels/requests' properties and updating virtio device
node names as per dtschema.

* tag 'juno-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno: Drop useless 'dma-channels/requests' properties
  arm64: dts: fvp: Align virtio device node names with dtschema
  arm64: dts: fvp: Add virtio-rng support
  arm64: dts: Add Arm corstone1000 platform support
  dt-bindings: Add Arm corstone1000 platform
  arm64: dts: juno: add CTI entries to device tree
  arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnel

Link: https://lore.kernel.org/r/20220504112917.3492009-1-sudeep.holla@arm.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 0fd8954b b30ae563

Documentation/devicetree/bindings/arm/arm,corstone1000.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/arm/arm,corstone1000.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: ARM Corstone1000 Device Tree Bindings



maintainers:

  - Vishnu Banavath <vishnu.banavath@arm.com>

  - Rui Miguel Silva <rui.silva@linaro.org>



description: |+

  ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that

  provides a flexible compute architecture that combines Cortex‑A and Cortex‑M

  processors.



  Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion

  systems for M-Class (or other) processors for adding sensors, connectivity,

  video, audio and machine learning at the edge System and security IPs to build

  a secure SoC for a range of rich IoT applications, for example gateways, smart

  cameras and embedded systems.



  Integrated Secure Enclave providing hardware Root of Trust and supporting

  seamless integration of the optional CryptoCell™-312 cryptographic

  accelerator.



properties:

  $nodename:

    const: '/'

  compatible:

    oneOf:

      - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA

          implementation of the Corstone1000 in the MPS3 prototyping board. See

          ARM document DAI0550.

        items:

          - const: arm,corstone1000-mps3

      - description: Corstone1000 FVP is the Fixed Virtual Platform

          implementation of this system. See ARM ecosystems FVP's.

        items:

          - const: arm,corstone1000-fvp



additionalProperties: true



...

arch/arm64/boot/dts/arm/Makefile

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@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju 
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb

dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb

arch/arm64/boot/dts/arm/corstone1000-fvp.dts

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// SPDX-License-Identifier: GPL-2.0 or MIT

/*

 * Copyright (c) 2022, Arm Limited. All rights reserved.

 * Copyright (c) 2022, Linaro Limited. All rights reserved.

 *

 */



/dts-v1/;



#include "corstone1000.dtsi"



/ {

	model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";

	compatible = "arm,corstone1000-fvp";



	smsc: ethernet@4010000 {

		compatible = "smsc,lan91c111";

		reg = <0x40100000 0x10000>;

		phy-mode = "mii";

		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

		reg-io-width = <2>;

	};



	vmmc_v3_3d: fixed_v3_3d {

		compatible = "regulator-fixed";

		regulator-name = "vmmc_supply";

		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		regulator-always-on;

	};



	sdmmc0: mmc@40300000 {

		compatible = "arm,pl18x", "arm,primecell";

		reg = <0x40300000 0x1000>;

		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;

		max-frequency = <12000000>;

		vmmc-supply = <&vmmc_v3_3d>;

		clocks = <&smbclk>, <&refclk100mhz>;

		clock-names = "smclk", "apb_pclk";

	};



	sdmmc1: mmc@50000000 {

		compatible = "arm,pl18x", "arm,primecell";

		reg = <0x50000000 0x10000>;

		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;

		max-frequency = <12000000>;

		vmmc-supply = <&vmmc_v3_3d>;

		clocks = <&smbclk>, <&refclk100mhz>;

		clock-names = "smclk", "apb_pclk";

	};

};

arch/arm64/boot/dts/arm/corstone1000-mps3.dts

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// SPDX-License-Identifier: GPL-2.0 or MIT

/*

 * Copyright (c) 2022, Arm Limited. All rights reserved.

 * Copyright (c) 2022, Linaro Limited. All rights reserved.

 *

 */



/dts-v1/;



#include "corstone1000.dtsi"



/ {

	model = "ARM Corstone1000 FPGA MPS3 board";

	compatible = "arm,corstone1000-mps3";



	smsc: ethernet@4010000 {

		compatible = "smsc,lan9220", "smsc,lan9115";

		reg = <0x40100000 0x10000>;

		phy-mode = "mii";

		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;

		reg-io-width = <2>;

		smsc,irq-push-pull;

	};



	usb_host: usb@40200000 {

		compatible = "nxp,usb-isp1763";

		reg = <0x40200000 0x100000>;

		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;

		bus-width = <16>;

		dr_mode = "host";

	};

};

arch/arm64/boot/dts/arm/corstone1000.dtsi

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// SPDX-License-Identifier: GPL-2.0 or MIT

/*

 * Copyright (c) 2022, Arm Limited. All rights reserved.

 * Copyright (c) 2022, Linaro Limited. All rights reserved.

 *

 */



#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	interrupt-parent = <&gic>;

	#address-cells = <1>;

	#size-cells = <1>;



	aliases {

		serial0 = &uart0;

		serial1 = &uart1;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		cpu: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a35";

			reg = <0>;

			next-level-cache = <&L2_0>;

		};

	};



	memory@88200000 {

		device_type = "memory";

		reg = <0x88200000 0x77e00000>;

	};



	gic: interrupt-controller@1c000000 {

		compatible = "arm,gic-400";

		#interrupt-cells = <3>;

		#address-cells = <0>;

		interrupt-controller;

		reg =	<0x1c010000 0x1000>,

			<0x1c02f000 0x2000>,

			<0x1c04f000 0x1000>,

			<0x1c06f000 0x2000>;

		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |

			      IRQ_TYPE_LEVEL_LOW)>;

	};



	L2_0: l2-cache0 {

		compatible = "cache";

		cache-level = <2>;

		cache-size = <0x80000>;

		cache-line-size = <64>;

		cache-sets = <1024>;

	};



	refclk100mhz: refclk100mhz {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <100000000>;

		clock-output-names = "apb_pclk";

	};



	smbclk: refclk24mhzx2 {

		/* Reference 24MHz clock x 2 */

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <48000000>;

		clock-output-names = "smclk";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts =	<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |

				 IRQ_TYPE_LEVEL_LOW)>,

				<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |

				 IRQ_TYPE_LEVEL_LOW)>,

				<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |

				 IRQ_TYPE_LEVEL_LOW)>,

				<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |

				 IRQ_TYPE_LEVEL_LOW)>;

	};



	uartclk: uartclk {

		/* UART clock - 50MHz */

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <50000000>;

		clock-output-names = "uartclk";

	};



	psci {

		compatible = "arm,psci-1.0", "arm,psci-0.2";

		method = "smc";

	};



	soc {

		compatible = "simple-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		interrupt-parent = <&gic>;

		ranges;



		timer@1a220000 {

			compatible = "arm,armv7-timer-mem";

			reg = <0x1a220000 0x1000>;

			#address-cells = <1>;

			#size-cells = <1>;

			clock-frequency = <50000000>;

			ranges;



			frame@1a230000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x1a230000 0x1000>;

			};

		};



		uart0: serial@1a510000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x1a510000 0x1000>;

			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&uartclk>, <&refclk100mhz>;

			clock-names = "uartclk", "apb_pclk";

		};



		uart1: serial@1a520000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x1a520000 0x1000>;

			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&uartclk>, <&refclk100mhz>;

			clock-names = "uartclk", "apb_pclk";

		};



		mhu_hse1: mailbox@1b820000 {

			compatible = "arm,mhuv2-tx", "arm,primecell";

			reg = <0x1b820000 0x1000>;

			clocks = <&refclk100mhz>;

			clock-names = "apb_pclk";

			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;

			#mbox-cells = <2>;

			arm,mhuv2-protocols = <0 0>;

			secure-status = "okay";     /* secure-world-only */

			status = "disabled";

		};



		mhu_seh1: mailbox@1b830000 {

			compatible = "arm,mhuv2-rx", "arm,primecell";

			reg = <0x1b830000 0x1000>;

			clocks = <&refclk100mhz>;

			clock-names = "apb_pclk";

			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;

			#mbox-cells = <2>;

			arm,mhuv2-protocols = <0 0>;

			secure-status = "okay";     /* secure-world-only */

			status = "disabled";

		};

	};

};