Unverified Commit e8bb8f19 authored by Witold Sadowski's avatar Witold Sadowski Committed by Mark Brown
Browse files

spi: cadence: Fix busy cycles calculation 



If xSPI is in x2/x4/x8 mode to calculate busy
cycles, busy bits count must be divided by the number
of lanes.
If opcommand is using 8 busy bits, but SPI is
in x4 mode, there will be only 2 busy cycles.

Signed-off-by: default avatarWitold Sadowski <wsadowski@marvell.com>
Reviewed-by: default avatarChandrakala Chavva <cchavva@marvell.com>
Reviewed-by: default avatarSunil Kovvuri Goutham <sgoutham@marvell.com>
Link: https://lore.kernel.org/r/20221219144254.20883-2-wsadowski@marvell.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent b24cded8

drivers/spi/spi-cadence-xspi.c

+4 −1
Original line number Original line Diff line number Diff line
@@ -177,7 +177,10 @@ 
#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \

#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_3(op) ( \

	FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \

	FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_DCNT_H, \

		((op)->data.nbytes >> 16) & 0xffff) | \

		((op)->data.nbytes >> 16) & 0xffff) | \

	FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, (op)->dummy.nbytes * 8))

	FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R3_NUM_OF_DUMMY, \

		  (op)->dummy.buswidth != 0 ? \

		  (((op)->dummy.nbytes * 8) / (op)->dummy.buswidth) : \

		  0))





#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \

#define CDNS_XSPI_CMD_FLD_DSEQ_CMD_4(op, chipsel) ( \

	FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \

	FIELD_PREP(CDNS_XSPI_CMD_DSEQ_R4_BANK, chipsel) | \