Commit e8aae154 authored by Peter Geis's avatar Peter Geis Committed by Lorenzo Pieralisi
Browse files

PCI: rockchip-dwc: Add legacy interrupt support 

The legacy interrupts on the rk356x PCIe controller are handled by a
single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip
driver to support the virtual domain.

Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com


Signed-off-by: default avatarPeter Geis <pgwipeout@gmail.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
parent 431e7d2e

drivers/pci/controller/dwc/pcie-dw-rockchip.c

+94 −2
Original line number Diff line number Diff line
@@ -10,9 +10,12 @@ 


#include <linux/clk.h>

#include <linux/gpio/consumer.h>

#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/mfd/syscon.h>

#include <linux/module.h>

#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/phy/phy.h>

#include <linux/platform_device.h>

#include <linux/regmap.h>
@@ -26,6 +29,7 @@ 
 */

#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))

#define HIWORD_UPDATE_BIT(val)	HIWORD_UPDATE(val, val)

#define HIWORD_DISABLE_BIT(val)	HIWORD_UPDATE(val, ~val)



#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
@@ -36,6 +40,8 @@ 
#define PCIE_LINKUP			(PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)

#define PCIE_L0S_ENTRY			0x11

#define PCIE_CLIENT_GENERAL_CONTROL	0x0

#define PCIE_CLIENT_INTR_STATUS_LEGACY	0x8

#define PCIE_CLIENT_INTR_MASK_LEGACY	0x1c

#define PCIE_CLIENT_GENERAL_DEBUG	0x104

#define PCIE_CLIENT_HOT_RESET_CTRL	0x180

#define PCIE_CLIENT_LTSSM_STATUS	0x300
@@ -51,6 +57,7 @@ struct rockchip_pcie { 
	struct reset_control		*rst;

	struct gpio_desc		*rst_gpio;

	struct regulator                *vpcie3v3;

	struct irq_domain		*irq_domain;

};



static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
@@ -65,6 +72,78 @@ static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, 
	writel_relaxed(val, rockchip->apb_base + reg);

}



static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)

{

	struct irq_chip *chip = irq_desc_get_chip(desc);

	struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);

	unsigned long reg, hwirq;



	chained_irq_enter(chip, desc);



	reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);



	for_each_set_bit(hwirq, &reg, 4)

		generic_handle_domain_irq(rockchip->irq_domain, hwirq);



	chained_irq_exit(chip, desc);

}



static void rockchip_intx_mask(struct irq_data *data)

{

	rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),

				 HIWORD_UPDATE_BIT(BIT(data->hwirq)),

				 PCIE_CLIENT_INTR_MASK_LEGACY);

};



static void rockchip_intx_unmask(struct irq_data *data)

{

	rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),

				 HIWORD_DISABLE_BIT(BIT(data->hwirq)),

				 PCIE_CLIENT_INTR_MASK_LEGACY);

};



static struct irq_chip rockchip_intx_irq_chip = {

	.name			= "INTx",

	.irq_mask		= rockchip_intx_mask,

	.irq_unmask		= rockchip_intx_unmask,

	.flags			= IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,

};



static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,

				  irq_hw_number_t hwirq)

{

	irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);

	irq_set_chip_data(irq, domain->host_data);



	return 0;

}



static const struct irq_domain_ops intx_domain_ops = {

	.map = rockchip_pcie_intx_map,

};



static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)

{

	struct device *dev = rockchip->pci.dev;

	struct device_node *intc;



	intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");

	if (!intc) {

		dev_err(dev, "missing child interrupt-controller node\n");

		return -EINVAL;

	}



	rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,

						    &intx_domain_ops, rockchip);

	of_node_put(intc);

	if (!rockchip->irq_domain) {

		dev_err(dev, "failed to get a INTx IRQ domain\n");

		return -EINVAL;

	}



	return 0;

}



static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)

{

	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
@@ -111,7 +190,20 @@ static int rockchip_pcie_host_init(struct pcie_port *pp) 
{

	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);

	struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);

	struct device *dev = rockchip->pci.dev;

	u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);

	int irq, ret;



	irq = of_irq_get_byname(dev->of_node, "legacy");

	if (irq < 0)

		return irq;



	ret = rockchip_pcie_init_irq_domain(rockchip);

	if (ret < 0)

		dev_err(dev, "failed to init irq domain\n");



	irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,

					 rockchip);



	/* LTSSM enable control mode */

	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);