Commit e8a7fdc5 authored by Sivaprakash Murugesan's avatar Sivaprakash Murugesan Committed by Bjorn Andersson
Browse files

arm64: dts: ipq8074: qcom: Re-arrange dts nodes based on address 



This patch re-arranges ipq8074 device nodes based on node address
followed by node names followed by node labels.

Suggested-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Link: https://lore.kernel.org/r/1586572830-22727-1-git-send-email-sivaprak@codeaurora.org


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 5a307c66

arch/arm64/boot/dts/qcom/ipq8074-hk01.dts

+55 −57
Original line number Diff line number Diff line
@@ -24,13 +24,13 @@ 
		device_type = "memory";

		reg = <0x0 0x40000000 0x0 0x20000000>;

	};

};



	soc {

		serial@78b3000 {

&blsp1_i2c2 {

	status = "ok";

};



		spi@78b5000 {

&blsp1_spi1 {

	status = "ok";



	m25p80@0 {
@@ -42,45 +42,43 @@ 
	};

};



		serial@78b1000 {

&blsp1_uart3 {

	status = "ok";

};



		i2c@78b6000 {

&blsp1_uart5 {

	status = "ok";

};



		dma@7984000 {

&pcie0 {

	status = "ok";

	perst-gpio = <&tlmm 61 0x1>;

};



		nand@79b0000 {

&pcie1 {

	status = "ok";



			nand@0 {

				reg = <0>;

				nand-ecc-strength = <4>;

				nand-ecc-step-size = <512>;

				nand-bus-width = <8>;

			};

	perst-gpio = <&tlmm 58 0x1>;

};



		phy@86000 {

&pcie_phy0 {

	status = "ok";

};



		phy@8e000 {

&pcie_phy1 {

	status = "ok";

};



		pci@20000000 {

&qpic_bam {

	status = "ok";

			perst-gpio = <&tlmm 58 0x1>;

};



		pci@10000000 {

&qpic_nand {

	status = "ok";

			perst-gpio = <&tlmm 61 0x1>;

		};



	nand@0 {

		reg = <0>;

		nand-ecc-strength = <4>;

		nand-ecc-step-size = <512>;

		nand-bus-width = <8>;

	};

};

arch/arm64/boot/dts/qcom/ipq8074.dtsi

+237 −237
Original line number Diff line number Diff line
@@ -10,15 +10,111 @@ 
	model = "Qualcomm Technologies, Inc. IPQ8074";

	compatible = "qcom,ipq8074";



	clocks {

		sleep_clk: sleep_clk {

			compatible = "fixed-clock";

			clock-frequency = <32000>;

			#clock-cells = <0>;

		};



		xo: xo {

			compatible = "fixed-clock";

			clock-frequency = <19200000>;

			#clock-cells = <0>;

		};

	};



	cpus {

		#address-cells = <0x1>;

		#size-cells = <0x0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x1>;

			next-level-cache = <&L2_0>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x2>;

			next-level-cache = <&L2_0>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x3>;

			next-level-cache = <&L2_0>;

		};



		L2_0: l2-cache {

			compatible = "cache";

			cache-level = <0x2>;

		};

	};



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	soc: soc {

		#address-cells = <0x1>;

		#size-cells = <0x1>;

		ranges = <0 0 0 0xffffffff>;

		compatible = "simple-bus";



		pcie_phy0: phy@86000 {

			compatible = "qcom,ipq8074-qmp-pcie-phy";

			reg = <0x00086000 0x1000>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;

			clock-names = "pipe_clk";

			clock-output-names = "pcie20_phy0_pipe_clk";



			resets = <&gcc GCC_PCIE0_PHY_BCR>,

				<&gcc GCC_PCIE0PHY_PHY_BCR>;

			reset-names = "phy",

				      "common";

			status = "disabled";

		};



		pcie_phy1: phy@8e000 {

			compatible = "qcom,ipq8074-qmp-pcie-phy";

			reg = <0x0008e000 0x1000>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;

			clock-names = "pipe_clk";

			clock-output-names = "pcie20_phy1_pipe_clk";



			resets = <&gcc GCC_PCIE1_PHY_BCR>,

				<&gcc GCC_PCIE1PHY_PHY_BCR>;

			reset-names = "phy",

				      "common";

			status = "disabled";

		};



		tlmm: pinctrl@1000000 {

			compatible = "qcom,ipq8074-pinctrl";

			reg = <0x1000000 0x300000>;

			reg = <0x01000000 0x300000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			gpio-ranges = <&tlmm 0 0 70>;
@@ -66,102 +162,16 @@ 
			};

		};



		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;

			#interrupt-cells = <0x3>;

			reg = <0xb000000 0x1000>, <0xb002000 0x1000>;

		};



		timer {

			compatible = "arm,armv8-timer";

			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		};



		timer@b120000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0xb120000 0x1000>;

			clock-frequency = <19200000>;



			frame@b120000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb121000 0x1000>,

				      <0xb122000 0x1000>;

			};



			frame@b123000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb123000 0x1000>;

				status = "disabled";

			};



			frame@b124000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb124000 0x1000>;

				status = "disabled";

			};



			frame@b125000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb125000 0x1000>;

				status = "disabled";

			};



			frame@b126000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb126000 0x1000>;

				status = "disabled";

			};



			frame@b127000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb127000 0x1000>;

				status = "disabled";

			};



			frame@b128000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0xb128000 0x1000>;

				status = "disabled";

			};

		};



		gcc: gcc@1800000 {

			compatible = "qcom,gcc-ipq8074";

			reg = <0x1800000 0x80000>;

			reg = <0x01800000 0x80000>;

			#clock-cells = <0x1>;

			#reset-cells = <0x1>;

		};



		blsp1_uart5: serial@78b3000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x78b3000 0x200>;

			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-0 = <&serial_4_pins>;

			pinctrl-names = "default";

			status = "disabled";

		};



		blsp_dma: dma@7884000 {

			compatible = "qcom,bam-v1.7.0";

			reg = <0x7884000 0x2b000>;

			reg = <0x07884000 0x2b000>;

			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "bam_clk";
@@ -171,7 +181,7 @@ 


		blsp1_uart1: serial@78af000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x78af000 0x200>;

			reg = <0x078af000 0x200>;

			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;
@@ -181,7 +191,7 @@ 


		blsp1_uart3: serial@78b1000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x78b1000 0x200>;

			reg = <0x078b1000 0x200>;

			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,

				<&gcc GCC_BLSP1_AHB_CLK>;
@@ -194,11 +204,23 @@ 
			status = "disabled";

		};



		blsp1_uart5: serial@78b3000 {

			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";

			reg = <0x078b3000 0x200>;

			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,

				 <&gcc GCC_BLSP1_AHB_CLK>;

			clock-names = "core", "iface";

			pinctrl-0 = <&serial_4_pins>;

			pinctrl-names = "default";

			status = "disabled";

		};



		blsp1_spi1: spi@78b5000 {

			compatible = "qcom,spi-qup-v2.2.1";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x78b5000 0x600>;

			reg = <0x078b5000 0x600>;

			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;

			spi-max-frequency = <50000000>;

			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
@@ -215,7 +237,7 @@ 
			compatible = "qcom,i2c-qup-v2.2.1";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x78b6000 0x600>;

			reg = <0x078b6000 0x600>;

			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
@@ -232,7 +254,7 @@ 
			compatible = "qcom,i2c-qup-v2.2.1";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x78b7000 0x600>;

			reg = <0x078b7000 0x600>;

			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_BLSP1_AHB_CLK>,

				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
@@ -245,7 +267,7 @@ 


		qpic_bam: dma@7984000 {

			compatible = "qcom,bam-v1.7.0";

			reg = <0x7984000 0x1a000>;

			reg = <0x07984000 0x1a000>;

			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&gcc GCC_QPIC_AHB_CLK>;

			clock-names = "bam_clk";
@@ -256,7 +278,7 @@ 


		qpic_nand: nand@79b0000 {

			compatible = "qcom,ipq8074-nand";

			reg = <0x79b0000 0x10000>;

			reg = <0x079b0000 0x10000>;

			#address-cells = <1>;

			#size-cells = <0>;

			clocks = <&gcc GCC_QPIC_CLK>,
@@ -272,104 +294,85 @@ 
			status = "disabled";

		};



		pcie_phy0: phy@86000 {

			compatible = "qcom,ipq8074-qmp-pcie-phy";

			reg = <0x86000 0x1000>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;

			clock-names = "pipe_clk";

			clock-output-names = "pcie20_phy0_pipe_clk";

		intc: interrupt-controller@b000000 {

			compatible = "qcom,msm-qgic2";

			interrupt-controller;

			#interrupt-cells = <0x3>;

			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;

		};



			resets = <&gcc GCC_PCIE0_PHY_BCR>,

				<&gcc GCC_PCIE0PHY_PHY_BCR>;

			reset-names = "phy",

				      "common";

			status = "disabled";

		timer {

			compatible = "arm,armv8-timer";

			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

		};



		pcie0: pci@20000000 {

			compatible = "qcom,pcie-ipq8074";

			reg =  <0x20000000 0xf1d

				0x20000f20 0xa8

				0x80000 0x2000

				0x20100000 0x1000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;

		timer@b120000 {

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;

			compatible = "arm,armv7-timer-mem";

			reg = <0x0b120000 0x1000>;

			clock-frequency = <19200000>;



			phys = <&pcie_phy0>;

			phy-names = "pciephy";

			frame@b120000 {

				frame-number = <0>;

				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b121000 0x1000>,

				      <0x0b122000 0x1000>;

			};



			ranges = <0x81000000 0 0x20200000 0x20200000

				  0 0x100000   /* downstream I/O */

				  0x82000000 0 0x20300000 0x20300000

				  0 0xd00000>; /* non-prefetchable memory */

			frame@b123000 {

				frame-number = <1>;

				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b123000 0x1000>;

				status = "disabled";

			};



			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 75

					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 78

					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 79

					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 83

					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */

			frame@b124000 {

				frame-number = <2>;

				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b124000 0x1000>;

				status = "disabled";

			};



			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,

				 <&gcc GCC_PCIE0_AXI_M_CLK>,

				 <&gcc GCC_PCIE0_AXI_S_CLK>,

				 <&gcc GCC_PCIE0_AHB_CLK>,

				 <&gcc GCC_PCIE0_AUX_CLK>;

			frame@b125000 {

				frame-number = <3>;

				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b125000 0x1000>;

				status = "disabled";

			};



			clock-names = "iface",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "aux";

			resets = <&gcc GCC_PCIE0_PIPE_ARES>,

				 <&gcc GCC_PCIE0_SLEEP_ARES>,

				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,

				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,

				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,

				 <&gcc GCC_PCIE0_AHB_ARES>,

				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;

			reset-names = "pipe",

				      "sleep",

				      "sticky",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "axi_m_sticky";

			frame@b126000 {

				frame-number = <4>;

				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b126000 0x1000>;

				status = "disabled";

			};



		pcie_phy1: phy@8e000 {

			compatible = "qcom,ipq8074-qmp-pcie-phy";

			reg = <0x8e000 0x1000>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;

			clock-names = "pipe_clk";

			clock-output-names = "pcie20_phy1_pipe_clk";

			frame@b127000 {

				frame-number = <5>;

				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b127000 0x1000>;

				status = "disabled";

			};



			resets = <&gcc GCC_PCIE1_PHY_BCR>,

				<&gcc GCC_PCIE1PHY_PHY_BCR>;

			reset-names = "phy",

				      "common";

			frame@b128000 {

				frame-number = <6>;

				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

				reg = <0x0b128000 0x1000>;

				status = "disabled";

			};

		};



		pcie1: pci@10000000 {

			compatible = "qcom,pcie-ipq8074";

			reg =  <0x10000000 0xf1d

				0x10000f20 0xa8

				0x88000 0x2000

				0x00088000 0x2000

				0x10100000 0x1000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";
@@ -426,71 +429,68 @@ 
				      "axi_m_sticky";

			status = "disabled";

		};

	};



	cpus {

		#address-cells = <0x1>;

		#size-cells = <0x0>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			reg = <0x0>;

			next-level-cache = <&L2_0>;

			enable-method = "psci";

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x1>;

			next-level-cache = <&L2_0>;

		};



		CPU2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x2>;

			next-level-cache = <&L2_0>;

		};



		CPU3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x3>;

			next-level-cache = <&L2_0>;

		};

		pcie0: pci@20000000 {

			compatible = "qcom,pcie-ipq8074";

			reg =  <0x20000000 0xf1d

				0x20000f20 0xa8

				0x00080000 0x2000

				0x20100000 0x1000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;



		L2_0: l2-cache {

			compatible = "cache";

			cache-level = <0x2>;

		};

	};

			phys = <&pcie_phy0>;

			phy-names = "pciephy";



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};

			ranges = <0x81000000 0 0x20200000 0x20200000

				  0 0x100000   /* downstream I/O */

				  0x82000000 0 0x20300000 0x20300000

				  0 0xd00000>; /* non-prefetchable memory */



	pmu {

		compatible = "arm,armv8-pmuv3";

		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

	};

			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 75

					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 78

					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 79

					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 83

					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



	clocks {

		sleep_clk: sleep_clk {

			compatible = "fixed-clock";

			clock-frequency = <32000>;

			#clock-cells = <0>;

		};

			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,

				 <&gcc GCC_PCIE0_AXI_M_CLK>,

				 <&gcc GCC_PCIE0_AXI_S_CLK>,

				 <&gcc GCC_PCIE0_AHB_CLK>,

				 <&gcc GCC_PCIE0_AUX_CLK>;



		xo: xo {

			compatible = "fixed-clock";

			clock-frequency = <19200000>;

			#clock-cells = <0>;

			clock-names = "iface",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "aux";

			resets = <&gcc GCC_PCIE0_PIPE_ARES>,

				 <&gcc GCC_PCIE0_SLEEP_ARES>,

				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,

				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,

				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,

				 <&gcc GCC_PCIE0_AHB_ARES>,

				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;

			reset-names = "pipe",

				      "sleep",

				      "sticky",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "axi_m_sticky";

			status = "disabled";

		};

	};

};