Unverified Commit e8a62cc2 authored by Alexandre Ghiti's avatar Alexandre Ghiti Committed by Palmer Dabbelt
Browse files

riscv: Implement sv48 support 



By adding a new 4th level of page table, give the possibility to 64bit
kernel to address 2^48 bytes of virtual address: in practice, that offers
128TB of virtual address space to userspace and allows up to 64TB of
physical memory.

If the underlying hardware does not support sv48, we will automatically
fallback to a standard 3-level page table by folding the new PUD level into
PGDIR level. In order to detect HW capabilities at runtime, we
use SATP feature that ignores writes with an unsupported mode.

Signed-off-by: default avatarAlexandre Ghiti <alexandre.ghiti@canonical.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 60639f74

arch/riscv/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -150,7 +150,7 @@ config PAGE_OFFSET 
	hex

	default 0xC0000000 if 32BIT

	default 0x80000000 if 64BIT && !MMU

	default 0xffffffd800000000 if 64BIT

	default 0xffffaf8000000000 if 64BIT



config KASAN_SHADOW_OFFSET

	hex
@@ -201,7 +201,7 @@ config FIX_EARLYCON_MEM 


config PGTABLE_LEVELS

	int

	default 3 if 64BIT

	default 4 if 64BIT

	default 2



config LOCKDEP_SUPPORT

arch/riscv/include/asm/csr.h

+1 −2
Original line number Diff line number Diff line
@@ -40,14 +40,13 @@ 
#ifndef CONFIG_64BIT

#define SATP_PPN	_AC(0x003FFFFF, UL)

#define SATP_MODE_32	_AC(0x80000000, UL)

#define SATP_MODE	SATP_MODE_32

#define SATP_ASID_BITS	9

#define SATP_ASID_SHIFT	22

#define SATP_ASID_MASK	_AC(0x1FF, UL)

#else

#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)

#define SATP_MODE_39	_AC(0x8000000000000000, UL)

#define SATP_MODE	SATP_MODE_39

#define SATP_MODE_48	_AC(0x9000000000000000, UL)

#define SATP_ASID_BITS	16

#define SATP_ASID_SHIFT	44

#define SATP_ASID_MASK	_AC(0xFFFF, UL)

arch/riscv/include/asm/fixmap.h

+1 −0
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ enum fixed_addresses { 
	FIX_HOLE,

	FIX_PTE,

	FIX_PMD,

	FIX_PUD,

	FIX_TEXT_POKE1,

	FIX_TEXT_POKE0,

	FIX_EARLYCON_MEM_BASE,

arch/riscv/include/asm/kasan.h

+5 −1
Original line number Diff line number Diff line
@@ -28,7 +28,11 @@ 
#define KASAN_SHADOW_SCALE_SHIFT	3



#define KASAN_SHADOW_SIZE	(UL(1) << ((VA_BITS - 1) - KASAN_SHADOW_SCALE_SHIFT))

#define KASAN_SHADOW_START	(KASAN_SHADOW_END - KASAN_SHADOW_SIZE)

/*

 * Depending on the size of the virtual address space, the region may not be

 * aligned on PGDIR_SIZE, so force its alignment to ease its population.

 */

#define KASAN_SHADOW_START	((KASAN_SHADOW_END - KASAN_SHADOW_SIZE) & PGDIR_MASK)

#define KASAN_SHADOW_END	MODULES_LOWEST_VADDR

#define KASAN_SHADOW_OFFSET	_AC(CONFIG_KASAN_SHADOW_OFFSET, UL)

arch/riscv/include/asm/page.h

+14 −0
Original line number Diff line number Diff line
@@ -31,7 +31,20 @@ 
 * When not using MMU this corresponds to the first free page in

 * physical memory (aligned on a page boundary).

 */

#ifdef CONFIG_64BIT

#ifdef CONFIG_MMU

#define PAGE_OFFSET		kernel_map.page_offset

#else

#define PAGE_OFFSET		_AC(CONFIG_PAGE_OFFSET, UL)

#endif

/*

 * By default, CONFIG_PAGE_OFFSET value corresponds to SV48 address space so

 * define the PAGE_OFFSET value for SV39.

 */

#define PAGE_OFFSET_L3		_AC(0xffffffd800000000, UL)

#else

#define PAGE_OFFSET		_AC(CONFIG_PAGE_OFFSET, UL)

#endif /* CONFIG_64BIT */



#ifndef __ASSEMBLY__
@@ -84,6 +97,7 @@ extern unsigned long riscv_pfn_base; 
#endif /* CONFIG_MMU */



struct kernel_mapping {

	unsigned long page_offset;

	unsigned long virt_addr;

	uintptr_t phys_addr;

	uintptr_t size;