Commit e89d890c authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: update dio for two pixel per container case 



[why]
Processing rate of the DP encoder, must be programmed to be the same as
DIG_FIFO_OUTPUT_ PROCESSING_MODE in DP mode
0: 1 pixel per cycle
1: 2 pixel per cycle

Reviewed-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ac84304d

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dio_stream_encoder.c

+5 −0
Original line number Diff line number Diff line
@@ -286,6 +286,7 @@ static void enc32_stream_encoder_dp_unblank( 
		uint32_t n_vid = 0x8000;

		uint32_t m_vid;

		uint32_t n_multiply = 0;

		uint32_t pix_per_cycle = 0;

		uint64_t m_vid_l = n_vid;



		/* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */
@@ -320,6 +321,10 @@ static void enc32_stream_encoder_dp_unblank( 
		REG_UPDATE_2(DP_VID_TIMING,

				DP_VID_M_N_GEN_EN, 1,

				DP_VID_N_MUL, n_multiply);



		REG_UPDATE(DP_PIXEL_FORMAT,

				DP_PIXEL_PER_CYCLE_PROCESSING_MODE,

				pix_per_cycle);

	}



	/* make sure stream is disabled before resetting steer fifo */