Commit e8789ab7 authored by Oliver Upton's avatar Oliver Upton
Browse files

Merge branch kvm-arm64/virtual-cache-geometry into kvmarm/next 



* kvm-arm64/virtual-cache-geometry:
  : Virtualized cache geometry for KVM guests, courtesy of Akihiko Odaki.
  :
  : KVM/arm64 has always exposed the host cache geometry directly to the
  : guest, even though non-secure software should never perform CMOs by
  : Set/Way. This was slightly wrong, as the cache geometry was derived from
  : the PE on which the vCPU thread was running and not a sanitized value.
  :
  : All together this leads to issues migrating VMs on heterogeneous
  : systems, as the cache geometry saved/restored could be inconsistent.
  :
  : KVM/arm64 now presents 1 level of cache with 1 set and 1 way. The cache
  : geometry is entirely controlled by userspace, such that migrations from
  : older kernels continue to work.
  KVM: arm64: Mark some VM-scoped allocations as __GFP_ACCOUNT
  KVM: arm64: Normalize cache configuration
  KVM: arm64: Mask FEAT_CCIDX
  KVM: arm64: Always set HCR_TID2
  arm64/cache: Move CLIDR macro definitions
  arm64/sysreg: Add CCSIDR2_EL1
  arm64/sysreg: Convert CCSIDR_EL1 to automatic generation
  arm64: Allow the definition of UNKNOWN system register fields

Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parents 619cec00 5f623a59

arch/arm64/include/asm/cache.h

+9 −0
Original line number Diff line number Diff line
@@ -16,6 +16,15 @@ 
#define CLIDR_LOC(clidr)	(((clidr) >> CLIDR_LOC_SHIFT) & 0x7)

#define CLIDR_LOUIS(clidr)	(((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)



/* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */

#define CLIDR_CTYPE_SHIFT(level)	(3 * (level - 1))

#define CLIDR_CTYPE_MASK(level)		(7 << CLIDR_CTYPE_SHIFT(level))

#define CLIDR_CTYPE(clidr, level)	\

	(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))



/* Ttypen, bits [2(n - 1) + 34 : 2(n - 1) + 33], for n = 1 to 7 */

#define CLIDR_TTYPE_SHIFT(level)	(2 * ((level) - 1) + CLIDR_EL1_Ttypen_SHIFT)



/*

 * Memory returned by kmalloc() may be used for DMA, so we must make

 * sure that all such allocations are cache aligned. Otherwise,

arch/arm64/include/asm/kvm_arm.h

+2 −1
Original line number Diff line number Diff line
@@ -81,11 +81,12 @@ 
 * SWIO:	Turn set/way invalidates into set/way clean+invalidate

 * PTW:		Take a stage2 fault if a stage1 walk steps in device memory

 * TID3:	Trap EL1 reads of group 3 ID registers

 * TID2:	Trap CTR_EL0, CCSIDR2_EL1, CLIDR_EL1, and CSSELR_EL1

 */

#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \

			 HCR_BSU_IS | HCR_FB | HCR_TACR | \

			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \

			 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 )

			 HCR_FMO | HCR_IMO | HCR_PTW | HCR_TID3 | HCR_TID2)

#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)

#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)

#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)

arch/arm64/include/asm/kvm_emulate.h

+0 −4
Original line number Diff line number Diff line
@@ -88,10 +88,6 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu) 
	if (vcpu_el1_is_32bit(vcpu))

		vcpu->arch.hcr_el2 &= ~HCR_RW;



	if (cpus_have_const_cap(ARM64_MISMATCHED_CACHE_TYPE) ||

	    vcpu_el1_is_32bit(vcpu))

		vcpu->arch.hcr_el2 |= HCR_TID2;



	if (kvm_has_mte(vcpu->kvm))

		vcpu->arch.hcr_el2 |= HCR_ATA;

}

arch/arm64/include/asm/kvm_host.h

+4 −2
Original line number Diff line number Diff line
@@ -252,6 +252,7 @@ struct kvm_vcpu_fault_info { 
enum vcpu_sysreg {

	__INVALID_SYSREG__,   /* 0 is reserved as an invalid value */

	MPIDR_EL1,	/* MultiProcessor Affinity Register */

	CLIDR_EL1,	/* Cache Level ID Register */

	CSSELR_EL1,	/* Cache Size Selection Register */

	SCTLR_EL1,	/* System Control Register */

	ACTLR_EL1,	/* Auxiliary Control Register */
@@ -501,6 +502,9 @@ struct kvm_vcpu_arch { 
		u64 last_steal;

		gpa_t base;

	} steal;



	/* Per-vcpu CCSIDR override or NULL */

	u32 *ccsidr;

};



/*
@@ -705,7 +709,6 @@ static inline bool __vcpu_read_sys_reg_from_cpu(int reg, u64 *val) 
		return false;



	switch (reg) {

	case CSSELR_EL1:	*val = read_sysreg_s(SYS_CSSELR_EL1);	break;

	case SCTLR_EL1:		*val = read_sysreg_s(SYS_SCTLR_EL12);	break;

	case CPACR_EL1:		*val = read_sysreg_s(SYS_CPACR_EL12);	break;

	case TTBR0_EL1:		*val = read_sysreg_s(SYS_TTBR0_EL12);	break;
@@ -750,7 +753,6 @@ static inline bool __vcpu_write_sys_reg_to_cpu(u64 val, int reg) 
		return false;



	switch (reg) {

	case CSSELR_EL1:	write_sysreg_s(val, SYS_CSSELR_EL1);	break;

	case SCTLR_EL1:		write_sysreg_s(val, SYS_SCTLR_EL12);	break;

	case CPACR_EL1:		write_sysreg_s(val, SYS_CPACR_EL12);	break;

	case TTBR0_EL1:		write_sysreg_s(val, SYS_TTBR0_EL12);	break;

arch/arm64/include/asm/sysreg.h

+0 −1
Original line number Diff line number Diff line
@@ -404,7 +404,6 @@ 


#define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)



#define SYS_CCSIDR_EL1			sys_reg(3, 1, 0, 0, 0)

#define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)



#define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)