Commit e848edae authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
Browse files

clk: tegra: Add stubs needed for compile-testing 



Add stubs needed for compile-testing of Tegra memory drivers.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 4782c0a5

drivers/soc/tegra/pmc.c

+0 −5
Original line number Diff line number Diff line
@@ -743,11 +743,6 @@ static int tegra_powergate_enable_clocks(struct tegra_powergate *pg) 
	return err;

}



int __weak tegra210_clk_handle_mbist_war(unsigned int id)

{

	return 0;

}



static int tegra_powergate_power_up(struct tegra_powergate *pg,

				    bool disable_clocks)

{

include/linux/clk/tegra.h

+79 −21
Original line number Diff line number Diff line
@@ -123,20 +123,6 @@ static inline void tegra_cpu_clock_resume(void) 
}

#endif



extern int tegra210_plle_hw_sequence_start(void);

extern bool tegra210_plle_hw_sequence_is_enabled(void);

extern void tegra210_xusb_pll_hw_control_enable(void);

extern void tegra210_xusb_pll_hw_sequence_start(void);

extern void tegra210_sata_pll_hw_control_enable(void);

extern void tegra210_sata_pll_hw_sequence_start(void);

extern void tegra210_set_sata_pll_seq_sw(bool state);

extern void tegra210_put_utmipll_in_iddq(void);

extern void tegra210_put_utmipll_out_iddq(void);

extern int tegra210_clk_handle_mbist_war(unsigned int id);

extern void tegra210_clk_emc_dll_enable(bool flag);

extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);

extern void tegra210_clk_emc_update_setting(u32 emc_src_value);



struct clk;

struct tegra_emc;
@@ -144,17 +130,10 @@ typedef long (tegra20_clk_emc_round_cb)(unsigned long rate, 
					unsigned long min_rate,

					unsigned long max_rate,

					void *arg);



void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,

					void *cb_arg);

int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);



typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc,

						    unsigned long rate);

typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc,

						      unsigned long rate);

void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,

				    tegra124_emc_complete_timing_change_cb *complete_cb);



struct tegra210_clk_emc_config {

	unsigned long rate;
@@ -176,8 +155,87 @@ struct tegra210_clk_emc_provider { 
			const struct tegra210_clk_emc_config *config);

};



#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)

void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,

					void *cb_arg);

int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);

#else

static inline void

tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,

				   void *cb_arg)

{

}



static inline int

tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same)

{

	return 0;

}

#endif



#ifdef CONFIG_TEGRA124_CLK_EMC

void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,

				    tegra124_emc_complete_timing_change_cb *complete_cb);

#else

static inline void

tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,

			       tegra124_emc_complete_timing_change_cb *complete_cb)

{

}

#endif



#ifdef CONFIG_ARCH_TEGRA_210_SOC

int tegra210_plle_hw_sequence_start(void);

bool tegra210_plle_hw_sequence_is_enabled(void);

void tegra210_xusb_pll_hw_control_enable(void);

void tegra210_xusb_pll_hw_sequence_start(void);

void tegra210_sata_pll_hw_control_enable(void);

void tegra210_sata_pll_hw_sequence_start(void);

void tegra210_set_sata_pll_seq_sw(bool state);

void tegra210_put_utmipll_in_iddq(void);

void tegra210_put_utmipll_out_iddq(void);

int tegra210_clk_handle_mbist_war(unsigned int id);

void tegra210_clk_emc_dll_enable(bool flag);

void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);

void tegra210_clk_emc_update_setting(u32 emc_src_value);



int tegra210_clk_emc_attach(struct clk *clk,

			    struct tegra210_clk_emc_provider *provider);

void tegra210_clk_emc_detach(struct clk *clk);

#else

static inline int tegra210_plle_hw_sequence_start(void)

{

	return 0;

}



static inline bool tegra210_plle_hw_sequence_is_enabled(void)

{

	return false;

}



static inline int tegra210_clk_handle_mbist_war(unsigned int id)

{

	return 0;

}



static inline int

tegra210_clk_emc_attach(struct clk *clk,

			struct tegra210_clk_emc_provider *provider)

{

	return 0;

}



static inline void tegra210_xusb_pll_hw_control_enable(void) {}

static inline void tegra210_xusb_pll_hw_sequence_start(void) {}

static inline void tegra210_sata_pll_hw_control_enable(void) {}

static inline void tegra210_sata_pll_hw_sequence_start(void) {}

static inline void tegra210_set_sata_pll_seq_sw(bool state) {}

static inline void tegra210_put_utmipll_in_iddq(void) {}

static inline void tegra210_put_utmipll_out_iddq(void) {}

static inline void tegra210_clk_emc_dll_enable(bool flag) {}

static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {}

static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {}

static inline void tegra210_clk_emc_detach(struct clk *clk) {}

#endif



#endif /* __LINUX_CLK_TEGRA_H_ */