Commit e827d149 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2022-04-20' of... 

Merge tag 'drm-intel-fixes-2022-04-20' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

- Unset enable_psr2_sel_fetch if PSR2 detection fails
- Fix to detect when VRR is turned off from panel settings

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YmAKuHwon7hGyIoC@jlahtine-mobl.ger.corp.intel.com
parents b2d229d4 bb023304

drivers/gpu/drm/i915/display/intel_dp.c

+11 −6
Original line number Diff line number Diff line
@@ -4383,13 +4383,20 @@ intel_dp_update_420(struct intel_dp *intel_dp) 
static void

intel_dp_set_edid(struct intel_dp *intel_dp)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct intel_connector *connector = intel_dp->attached_connector;

	struct edid *edid;

	bool vrr_capable;



	intel_dp_unset_edid(intel_dp);

	edid = intel_dp_get_edid(intel_dp);

	connector->detect_edid = edid;



	vrr_capable = intel_vrr_is_capable(&connector->base);

	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",

		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));

	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);



	intel_dp_update_dfp(intel_dp, edid);

	intel_dp_update_420(intel_dp);
@@ -4422,6 +4429,9 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) 


	intel_dp->dfp.ycbcr_444_to_420 = false;

	connector->base.ycbcr_420_allowed = false;



	drm_connector_set_vrr_capable_property(&connector->base,

					       false);

}



static int
@@ -4572,14 +4582,9 @@ static int intel_dp_get_modes(struct drm_connector *connector) 
	int num_modes = 0;



	edid = intel_connector->detect_edid;

	if (edid) {

	if (edid)

		num_modes = intel_connector_update_modes(connector, edid);



		if (intel_vrr_is_capable(connector))

			drm_connector_set_vrr_capable_property(connector,

							       true);

	}



	/* Also add fixed mode, which may or may not be present in EDID */

	if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&

	    intel_connector->panel.fixed_mode) {

drivers/gpu/drm/i915/display/intel_psr.c

+21 −17
Original line number Diff line number Diff line
@@ -887,6 +887,20 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
		return false;

	}



	/* Wa_16011303918:adl-p */

	if (crtc_state->vrr.enable &&

	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");

		return false;

	}



	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");

		return false;

	}



	if (HAS_PSR2_SEL_FETCH(dev_priv)) {

		if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) &&

		    !HAS_PSR_HW_TRACKING(dev_priv)) {
@@ -900,12 +914,12 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
	if (!crtc_state->enable_psr2_sel_fetch &&

	    IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_C0)) {

		drm_dbg_kms(&dev_priv->drm, "PSR2 HW tracking is not supported this Display stepping\n");

		return false;

		goto unsupported;

	}



	if (!psr2_granularity_check(intel_dp, crtc_state)) {

		drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n");

		return false;

		goto unsupported;

	}



	if (!crtc_state->enable_psr2_sel_fetch &&
@@ -914,25 +928,15 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, 
			    "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",

			    crtc_hdisplay, crtc_vdisplay,

			    psr_max_h, psr_max_v);

		return false;

	}



	if (!_compute_psr2_sdp_prior_scanline_indication(intel_dp, crtc_state)) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, PSR2 SDP indication do not fit in hblank\n");

		return false;

	}



	/* Wa_16011303918:adl-p */

	if (crtc_state->vrr.enable &&

	    IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {

		drm_dbg_kms(&dev_priv->drm,

			    "PSR2 not enabled, not compatible with HW stepping + VRR\n");

		return false;

		goto unsupported;

	}



	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);

	return true;



unsupported:

	crtc_state->enable_psr2_sel_fetch = false;

	return false;

}



void intel_psr_compute_config(struct intel_dp *intel_dp,