Commit e7f42648 authored by Wolfram Sang's avatar Wolfram Sang Committed by Wolfram Sang
Browse files

i2c: rcar: enable interrupts before starting transfer 



We want to enable the interrupts _before_ starting the transfer because
it is good programming style and also the proposed order in the R-Car
manual. There is no difference in practice because it doesn't matter in
which order both conditions appear if we wait for both to happen.

Signed-off-by: default avatarRyo Kataoka <ryo.kataoka.wt@renesas.com>
Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: default avatarUlrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: default avatarWolfram Sang <wsa@kernel.org>
parent c073b25d

drivers/i2c/busses/i2c-rcar.c

+3 −3
Original line number Diff line number Diff line
@@ -339,6 +339,9 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 
		priv->flags |= ID_LAST_MSG;



	rcar_i2c_write(priv, ICMAR, i2c_8bit_addr_from_msg(priv->msg));

	if (!priv->atomic_xfer)

		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);



	/*

	 * We don't have a test case but the HW engineers say that the write order

	 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
@@ -354,9 +357,6 @@ static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv) 
			rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);

		rcar_i2c_write(priv, ICMSR, 0);

	}



	if (!priv->atomic_xfer)

		rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);

}



static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)