spi: Pull in Atmel fix (e7cc4244) · Commits · EulixOS / Software / Kernel

drivers/spi/atmel-quadspi.c

+3 −6

Original line number	Diff line number	Diff line
		@@ -277,6 +277,9 @@ static int atmel_qspi_find_mode(const struct spi_mem_op *op)
		static bool atmel_qspi_supports_op(struct spi_mem *mem,
		const struct spi_mem_op *op)
		{
		if (!spi_mem_default_supports_op(mem, op))
		return false;

		if (atmel_qspi_find_mode(op) < 0)
		return false;

		@@ -285,12 +288,6 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem,
		op->dummy.nbytes == 0)
		return false;

		/* DTR ops not supported. */
		if (op->cmd.dtr \|\| op->addr.dtr \|\| op->dummy.dtr \|\| op->data.dtr)
		return false;
		if (op->cmd.nbytes != 1)
		return false;

		return true;
		}

drivers/spi/spi-bcm-qspi.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -1205,7 +1205,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
		addr = op->addr.val;
		len = op->data.nbytes;

		if (bcm_qspi_bspi_ver_three(qspi) == true) {
		if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) {
		/*
		* The address coming into this function is a raw flash offset.
		* But for BSPI <= V3, we need to convert it to a remapped BSPI
		@@ -1224,7 +1224,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
		len < 4)
		mspi_read = true;

		if (mspi_read)
		if (!has_bspi(qspi) \|\| mspi_read)
		return bcm_qspi_mspi_exec_mem_op(spi, op);

		ret = bcm_qspi_bspi_set_mode(qspi, op, 0);

drivers/spi/spi-cadence-quadspi.c

+29 −36

Original line number	Diff line number	Diff line
		@@ -19,6 +19,7 @@
		#include <linux/iopoll.h>
		#include <linux/jiffies.h>
		#include <linux/kernel.h>
		#include <linux/log2.h>
		#include <linux/module.h>
		#include <linux/of_device.h>
		#include <linux/of.h>
		@@ -102,12 +103,6 @@ struct cqspi_driver_platdata {
		#define CQSPI_TIMEOUT_MS 500
		#define CQSPI_READ_TIMEOUT_MS 10

		/* Instruction type */
		#define CQSPI_INST_TYPE_SINGLE 0
		#define CQSPI_INST_TYPE_DUAL 1
		#define CQSPI_INST_TYPE_QUAD 2
		#define CQSPI_INST_TYPE_OCTAL 3

		#define CQSPI_DUMMY_CLKS_PER_BYTE 8
		#define CQSPI_DUMMY_BYTES_MAX 4
		#define CQSPI_DUMMY_CLKS_MAX 31
		@@ -376,10 +371,6 @@ static unsigned int cqspi_calc_dummy(const struct spi_mem_op *op, bool dtr)
		static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
		const struct spi_mem_op *op)
		{
		f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE;
		f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE;
		f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;

		/*
		* For an op to be DTR, cmd phase along with every other non-empty
		* phase should have dtr field set to 1. If an op phase has zero
		@@ -389,32 +380,23 @@ static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,
		(!op->addr.nbytes \|\| op->addr.dtr) &&
		(!op->data.nbytes \|\| op->data.dtr);

		switch (op->data.buswidth) {
		case 0:
		break;
		case 1:
		f_pdata->data_width = CQSPI_INST_TYPE_SINGLE;
		break;
		case 2:
		f_pdata->data_width = CQSPI_INST_TYPE_DUAL;
		break;
		case 4:
		f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
		break;
		case 8:
		f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
		break;
		default:
		return -EINVAL;
		}
		f_pdata->inst_width = 0;
		if (op->cmd.buswidth)
		f_pdata->inst_width = ilog2(op->cmd.buswidth);

		f_pdata->addr_width = 0;
		if (op->addr.buswidth)
		f_pdata->addr_width = ilog2(op->addr.buswidth);

		f_pdata->data_width = 0;
		if (op->data.buswidth)
		f_pdata->data_width = ilog2(op->data.buswidth);

		/* Right now we only support 8-8-8 DTR mode. */
		if (f_pdata->dtr) {
		switch (op->cmd.buswidth) {
		case 0:
		break;
		case 8:
		f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL;
		break;
		default:
		return -EINVAL;
		@@ -422,9 +404,7 @@ static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,

		switch (op->addr.buswidth) {
		case 0:
		break;
		case 8:
		f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL;
		break;
		default:
		return -EINVAL;
		@@ -432,9 +412,7 @@ static int cqspi_set_protocol(struct cqspi_flash_pdata *f_pdata,

		switch (op->data.buswidth) {
		case 0:
		break;
		case 8:
		f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
		break;
		default:
		return -EINVAL;
		@@ -1437,9 +1415,24 @@ static bool cqspi_supports_mem_op(struct spi_mem *mem,
		all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&
		!op->data.dtr;

		/* Mixed DTR modes not supported. */
		if (!(all_true \|\| all_false))
		if (all_true) {
		/* Right now we only support 8-8-8 DTR mode. */
		if (op->cmd.nbytes && op->cmd.buswidth != 8)
		return false;
		if (op->addr.nbytes && op->addr.buswidth != 8)
		return false;
		if (op->data.nbytes && op->data.buswidth != 8)
		return false;
		} else if (all_false) {
		/* Only 1-1-X ops are supported without DTR */
		if (op->cmd.nbytes && op->cmd.buswidth > 1)
		return false;
		if (op->addr.nbytes && op->addr.buswidth > 1)
		return false;
		} else {
		/* Mixed DTR modes are not supported. */
		return false;
		}

		return spi_mem_default_supports_op(mem, op);
		}

drivers/spi/spi-intel-pci.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -72,6 +72,7 @@ static const struct pci_device_id intel_spi_pci_ids[] = {
		{ PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info },
		{ PCI_VDEVICE(INTEL, 0x51a4), (unsigned long)&cnl_info },
		{ PCI_VDEVICE(INTEL, 0x54a4), (unsigned long)&cnl_info },
		{ PCI_VDEVICE(INTEL, 0x7a24), (unsigned long)&cnl_info },
		{ PCI_VDEVICE(INTEL, 0x7aa4), (unsigned long)&cnl_info },
		{ PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info },
		{ PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info },

drivers/spi/spi-mtk-nor.c

+11 −1

Original line number	Diff line number	Diff line
		@@ -960,7 +960,17 @@ static int __maybe_unused mtk_nor_suspend(struct device *dev)

		static int __maybe_unused mtk_nor_resume(struct device *dev)
		{
		return pm_runtime_force_resume(dev);
		struct spi_controller *ctlr = dev_get_drvdata(dev);
		struct mtk_nor *sp = spi_controller_get_devdata(ctlr);
		int ret;

		ret = pm_runtime_force_resume(dev);
		if (ret)
		return ret;

		mtk_nor_init(sp);

		return 0;
		}

		static const struct dev_pm_ops mtk_nor_pm_ops = {