Commit e7a30ade authored by Wesley Chalmers's avatar Wesley Chalmers Committed by Alex Deucher
Browse files

Revert "drm/amd/display: Unblank hubp based on plane visibility" 



This reverts commit fd1c85d3

[Why]
We are not implementing the planned new HW sequence
to disable HUBP.

[How]
Revert most related changes to minimize possibility
of regression.

Signed-off-by: default avatarWesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: default avatarMartin Leung <Martin.Leung@amd.com>
Acked-by: default avatarQingqing Zhuo <Qingqing.Zhuo@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 29249676

drivers/gpu/drm/amd/display/dc/basics/dc_common.c

+6 −14
Original line number Diff line number Diff line
@@ -49,24 +49,20 @@ bool is_rgb_cspace(enum dc_color_space output_color_space) 
	}

}



bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

{

	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

		return true;

	if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))

		return true;

	if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))

	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

		return true;

	return false;

}



bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)

{

	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

		return true;

	if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))

		return true;

	if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))

	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

		return true;

	return false;

}
@@ -75,13 +71,9 @@ bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) 
{

	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)

		return true;

	if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))

		return true;

	if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))

		return true;

	if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))

	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))

		return true;

	if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))

	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))

		return true;

	return false;

}

drivers/gpu/drm/amd/display/dc/basics/dc_common.h

+2 −2
Original line number Diff line number Diff line
@@ -30,9 +30,9 @@ 


bool is_rgb_cspace(enum dc_color_space output_color_space);



bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);



bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);



bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -1575,7 +1575,7 @@ static void dcn20_update_dchubp_dpp( 






	if (is_pipe_tree_visible(pipe_ctx))

	if (pipe_ctx->update_flags.bits.enable)

		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);

}