Commit e79220db authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.7' of... 

Merge tag 'phy-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy

 into usb-next

Kishon writes:

phy: for 5.7

*) Rename and Re-design phy-cadence-dp driver to phy-cadence-torrent driver
*) Add new PHY driver for Qualcomm 28nm Hi-Speed USB PHY
*) Add new PHY driver for Qualcomm Super Speed PHY in QCS404
*) Add support for Qualcomm PCIe QMP/QHP PHY in SDM845 to phy-qcom-qmp driver
*) Add support for Qualcomm UFS PHY in MSM8996 to phy-qcom-qmp driver
*) Add support for an additional reference clock in Mediatek phy-mtk-tphy driver
*) Add support for configuring tuning parameters in Mediatek phy-mtk-tphy driver
*) Add support for GMII PHY in TI K3 AM654x/J721E SoCs to phy-gmii-sel driver
*) Add support for USB2 PHY in Amlogic A1 SoC Family to phy-meson-g12a-usb2
   driver
*) Add support for USB3/USB2/PCIe PHY in Socionext Pro5 SoC to
   phy-uniphier-usb3ss/phy-uniphier-usb3hs/phy-uniphier-pcie driver respectively
*) Add support for QUSB2 PHY in Qualcomm SC7180 in driver
*) Convert dt-bindings of Cadence DP, Qualcomm QUSB2 to YAML format

Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>

* tag 'phy-for-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (52 commits)
  phy: qcom-qusb2: Add new overriding tuning parameters in QUSB2 V2 PHY
  phy: qcom-qusb2: Add support for overriding tuning parameters in QUSB2 V2 PHY
  dt-bindings: phy: qcom-qusb2: Add support for overriding Phy tuning parameters
  phy: qcom-qusb2: Add generic QUSB2 V2 PHY support
  dt-bindings: phy: qcom,qusb2: Add compatibles for QUSB2 V2 phy and SC7180
  dt-bindings: phy: qcom,qusb2: Convert QUSB2 phy bindings to yaml
  phy: rk-inno-usb2: Decrease verbosity of repeating log.
  phy: amlogic: Add Amlogic A1 USB2 PHY Driver
  dt-bindings: phy: Add Amlogic A1 USB2 PHY Bindings
  phy: ti: gmii-sel: add support for am654x/j721e soc
  dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc
  phy: qualcomm: usb: Add SuperSpeed PHY driver
  dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
  phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver
  dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding
  dt-bindings: phy: remove qcom-dwc3-usb-phy
  phy: phy-mtk-tphy: add a new reference clock
  phy: phy-mtk-tphy: remove unused u3phya_ref clock
  phy: phy-mtk-tphy: make the ref clock optional
  phy: phy-mtk-tphy: add a property for internal resistance
  ...
parents f62c1930 89d71537

Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml

+14 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ properties: 
  compatible:

    enum:

      - amlogic,meson-g12a-usb2-phy

      - amlogic,meson-a1-usb2-phy



  reg:

    maxItems: 1
@@ -49,6 +50,19 @@ required: 
  - reset-names

  - "#phy-cells"



if:

  properties:

    compatible:

      enum:

        - amlogic,meson-a1-usb-ctrl



then:

  properties:

    power-domains:

      maxItems: 1

  required:

    - power-domains



examples:

  - |

    phy@36000 {

Documentation/devicetree/bindings/phy/phy-cadence-dp.txt

deleted100644 → 0
+0 −30
Original line number Diff line number Diff line 
Cadence MHDP DisplayPort SD0801 PHY binding

===========================================



This binding describes the Cadence SD0801 PHY hardware included with

the Cadence MHDP DisplayPort controller.



-------------------------------------------------------------------------------

Required properties (controller (parent) node):

- compatible	: Should be "cdns,dp-phy"

- reg		: Defines the following sets of registers in the parent

		  mhdp device:

			- Offset of the DPTX PHY configuration registers

			- Offset of the SD0801 PHY configuration registers

- #phy-cells	: from the generic PHY bindings, must be 0.



Optional properties:

- num_lanes	: Number of DisplayPort lanes to use (1, 2 or 4)

- max_bit_rate	: Maximum DisplayPort link bit rate to use, in Mbps (2160,

		  2430, 2700, 3240, 4320, 5400 or 8100)

-------------------------------------------------------------------------------



Example:

	dp_phy: phy@f0fb030a00 {

		compatible = "cdns,dp-phy";

		reg = <0xf0 0xfb030a00 0x0 0x00000040>,

		      <0xf0 0xfb500000 0x0 0x00100000>;

		num_lanes = <4>;

		max_bit_rate = <8100>;

		#phy-cells = <0>;

	};

Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml

0 → 100644
+143 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Cadence Torrent SD0801 PHY binding for DisplayPort



description:

  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)

  hardware included with the Cadence MHDP DisplayPort controller.



maintainers:

  - Swapnil Jakhade <sjakhade@cadence.com>

  - Yuti Amonkar <yamonkar@cadence.com>



properties:

  compatible:

    enum:

      - cdns,torrent-phy

      - ti,j721e-serdes-10g



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



  clocks:

    maxItems: 1

    description:

      PHY reference clock. Must contain an entry in clock-names.



  clock-names:

    const: refclk



  reg:

    minItems: 1

    maxItems: 2

    items:

      - description: Offset of the Torrent PHY configuration registers.

      - description: Offset of the DPTX PHY configuration registers.



  reg-names:

    minItems: 1

    maxItems: 2

    items:

      - const: torrent_phy

      - const: dptx_phy



  resets:

    maxItems: 1

    description:

      Torrent PHY reset.

      See Documentation/devicetree/bindings/reset/reset.txt



patternProperties:

  '^phy@[0-7]+$':

    type: object

    description:

      Each group of PHY lanes with a single master lane should be represented as a sub-node.

    properties:

      reg:

        description:

          The master lane number. This is the lowest numbered lane in the lane group.



      resets:

        minItems: 1

        maxItems: 4

        description:

          Contains list of resets, one per lane, to get all the link lanes out of reset.



      "#phy-cells":

        const: 0



      cdns,phy-type:

        description:

          Specifies the type of PHY for which the group of PHY lanes is used.

          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [1, 2, 3, 4, 5, 6]



      cdns,num-lanes:

        description:

          Number of DisplayPort lanes.

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [1, 2, 4]

        default: 4



      cdns,max-bit-rate:

        description:

          Maximum DisplayPort link bit rate to use, in Mbps

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]

        default: 8100



    required:

      - reg

      - resets

      - "#phy-cells"

      - cdns,phy-type



    additionalProperties: false



required:

  - compatible

  - "#address-cells"

  - "#size-cells"

  - clocks

  - clock-names

  - reg

  - reg-names

  - resets



additionalProperties: false



examples:

  - |

    #include <dt-bindings/phy/phy.h>

    torrent_phy: torrent-phy@f0fb500000 {

          compatible = "cdns,torrent-phy";

          reg = <0xf0 0xfb500000 0x0 0x00100000>,

                <0xf0 0xfb030a00 0x0 0x00000040>;

          reg-names = "torrent_phy", "dptx_phy";

          resets = <&phyrst 0>;

          clocks = <&ref_clk>;

          clock-names = "refclk";

          #address-cells = <1>;

          #size-cells = <0>;

          torrent_phy_dp: phy@0 {

                    reg = <0>;

                    resets = <&phyrst 1>, <&phyrst 2>,

                             <&phyrst 3>, <&phyrst 4>;

                    #phy-cells = <0>;

                    cdns,phy-type = <PHY_TYPE_DP>;

                    cdns,num-lanes = <4>;

                    cdns,max-bit-rate = <8100>;

          };

    };

...

Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt

+22 −10
Original line number Diff line number Diff line
@@ -13,10 +13,16 @@ Required properties (controller (parent) node): 
		  "mediatek,mt8173-u3phy";

		  make use of "mediatek,generic-tphy-v1" on mt2701 instead and

		  "mediatek,generic-tphy-v2" on mt2712 instead.

 - clocks	: (deprecated, use port's clocks instead) a list of phandle +

		  clock-specifier pairs, one for each entry in clock-names

 - clock-names	: (deprecated, use port's one instead) must contain

		  "u3phya_ref": for reference clock of usb3.0 analog phy.



- #address-cells:	the number of cells used to represent physical

		base addresses.

- #size-cells:	the number of cells used to represent the size of an address.

- ranges:	the address mapping relationship to the parent, defined with

		- empty value: if optional 'reg' is used.

		- non-empty value: if optional 'reg' is not used. should set

			the child's base address to 0, the physical address

			within parent's address space, and the length of

			the address map.



Required nodes	: a sub-node is required for each port the controller

		  provides. Address range information including the usual
@@ -34,12 +40,6 @@ Optional properties (controller (parent) node): 


Required properties (port (child) node):

- reg		: address and length of the register set for the port.

- clocks	: a list of phandle + clock-specifier pairs, one for each

		  entry in clock-names

- clock-names	: must contain

		  "ref": 48M reference clock for HighSpeed analog phy; and 26M

			reference clock for SuperSpeed analog phy, sometimes is

			24M, 25M or 27M, depended on platform.

- #phy-cells	: should be 1 (See second example)

		  cell after port phandle is phy type from:

			- PHY_TYPE_USB2
@@ -48,10 +48,22 @@ Required properties (port (child) node): 
			- PHY_TYPE_SATA



Optional properties (PHY_TYPE_USB2 port (child) node):

- clocks	: a list of phandle + clock-specifier pairs, one for each

		  entry in clock-names

- clock-names	: may contain

		  "ref": 48M reference clock for HighSpeed (digital) phy; and 26M

			reference clock for SuperSpeed (digital) phy, sometimes is

			24M, 25M or 27M, depended on platform.

		  "da_ref": the reference clock of analog phy, used if the clocks

			of analog and digital phys are separated, otherwise uses

			"ref" clock only if needed.



- mediatek,eye-src	: u32, the value of slew rate calibrate

- mediatek,eye-vrt	: u32, the selection of VRT reference voltage

- mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage

- mediatek,bc12	: bool, enable BC12 of u2phy if support it

- mediatek,discth	: u32, the selection of disconnect threshold

- mediatek,intr	: u32, the selection of internal R (resistance)



Example:

Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml

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+185 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)



%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Qualcomm QUSB2 phy controller



maintainers:

  - Manu Gautam <mgautam@codeaurora.org>



description:

  QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.



properties:

  compatible:

    oneOf:

      - items:

        - enum:

          - qcom,msm8996-qusb2-phy

          - qcom,msm8998-qusb2-phy

      - items:

        - enum:

          - qcom,sc7180-qusb2-phy

          - qcom,sdm845-qusb2-phy

        - const: qcom,qusb2-v2-phy

  reg:

    maxItems: 1



  "#phy-cells":

    const: 0



  clocks:

    minItems: 2

    maxItems: 3

    items:

      - description: phy config clock

      - description: 19.2 MHz ref clk

      - description: phy interface clock (Optional)



  clock-names:

    minItems: 2

    maxItems: 3

    items:

      - const: cfg_ahb

      - const: ref

      - const: iface



  vdda-pll-supply:

     description:

       Phandle to 1.8V regulator supply to PHY refclk pll block.



  vdda-phy-dpdm-supply:

     description:

       Phandle to 3.1V regulator supply to Dp/Dm port signals.



  resets:

    maxItems: 1

    description:

      Phandle to reset to phy block.



  nvmem-cells:

    maxItems: 1

    description:

        Phandle to nvmem cell that contains 'HS Tx trim'

        tuning parameter value for qusb2 phy.



  qcom,tcsr-syscon:

    description:

        Phandle to TCSR syscon register region.

    $ref: /schemas/types.yaml#/definitions/phandle



if:

  properties:

    compatible:

      contains:

        const: qcom,qusb2-v2-phy

then:

  properties:

    qcom,imp-res-offset-value:

      description:

        It is a 6 bit value that specifies offset to be

        added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY

        tuning parameter that may vary for different boards of same SOC.

      allOf:

        - $ref: /schemas/types.yaml#/definitions/uint32

        - minimum: 0

          maximum: 63

          default: 0



    qcom,bias-ctrl-value:

      description:

        It is a 6 bit value that specifies bias-ctrl-value. It is a PHY

        tuning parameter that may vary for different boards of same SOC.

      allOf:

        - $ref: /schemas/types.yaml#/definitions/uint32

        - minimum: 0

          maximum: 63

          default: 0



    qcom,charge-ctrl-value:

     description:

        It is a 2 bit value that specifies charge-ctrl-value. It is a PHY

        tuning parameter that may vary for different boards of same SOC.

     allOf:

       - $ref: /schemas/types.yaml#/definitions/uint32

       - minimum: 0

         maximum: 3

         default: 0



    qcom,hstx-trim-value:

      description:

        It is a 4 bit value that specifies tuning for HSTX

        output current.

        Possible range is - 15mA to 24mA (stepsize of 600 uA).

        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.

      allOf:

        - $ref: /schemas/types.yaml#/definitions/uint32

        - minimum: 0

          maximum: 15

          default: 3



    qcom,preemphasis-level:

      description:

        It is a 2 bit value that specifies pre-emphasis level.

        Possible range is 0 to 15% (stepsize of 5%).

        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.

      allOf:

        - $ref: /schemas/types.yaml#/definitions/uint32

        - minimum: 0

          maximum: 3

          default: 2



    qcom,preemphasis-width:

      description:

        It is a 1 bit value that specifies how long the HSTX

        pre-emphasis (specified using qcom,preemphasis-level) must be in

        effect. Duration could be half-bit of full-bit.

        See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.

      allOf:

        - $ref: /schemas/types.yaml#/definitions/uint32

        - minimum: 0

          maximum: 1

          default: 0



    qcom,hsdisc-trim-value:

      description:

        It is a 2 bit value tuning parameter that control disconnect

        threshold and may vary for different boards of same SOC.

      allOf:

        - $ref: /schemas/types.yaml#/definitions/uint32

        - minimum: 0

          maximum: 3

          default: 0



required:

  - compatible

  - reg

  - "#phy-cells"

  - clocks

  - clock-names

  - vdda-pll-supply

  - vdda-phy-dpdm-supply

  - resets





examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-msm8996.h>

    hsusb_phy: phy@7411000 {

        compatible = "qcom,msm8996-qusb2-phy";

        reg = <0x7411000 0x180>;

        #phy-cells = <0>;



        clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,

                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;

        clock-names = "cfg_ahb", "ref";



        vdda-pll-supply = <&pm8994_l12>;

        vdda-phy-dpdm-supply = <&pm8994_l24>;



        resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;

        nvmem-cells = <&qusb2p_hstx_trim>;

    };