Commit e7904111 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'phy-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 

Pull phy updates from Vinod Koul:
 "This tme we have again a big pile of qcom-qmp-* changes, one new
  driver and bunch of new hardware support.

  New hardware support:

   - Allwinner H616 USB PHY and A100 DPHY support

   - TI J721s2, J784s4 and J721e support

   - Freescale i.MX8MP PCIe PHY support

   - New driver for Renesas Ethernet SERDES supporting R-Car S4-8

   - Qualcomm SM8450 PCIe1 PHY support in EP mode

   - Qualcomm SC8280XP PCIe PHY support (including x4 mode)

   - Fixed Qualcomm SC8280XP USB4-USB3-DP PHY DT bindings

  Updates:

   - A big pile of updates on qcom-qmp-* drivers following the driver
     split and reorganization merged earlier

   - Phy order of API calls documentation update"

* tag 'phy-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (174 commits)
  phy: ti: phy-j721e-wiz: add j721s2-wiz-10g module support
  dt-bindings: phy-j721e-wiz: add j721s2 compatible string
  phy: use devm_platform_get_and_ioremap_resource()
  phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant
  phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook
  phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last
  phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional
  dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant
  dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property
  phy: qcom-qmp-pcie: drop redundant clock allocation
  phy: qcom-qmp-usb: drop redundant clock allocation
  phy: qcom-qmp: drop unused type header
  phy: qcom-qmp-usb: drop sc8280xp reference-clock source
  dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: drop reference-clock source
  phy: qcom-qmp-combo: add support for updated sc8280xp binding
  phy: qcom-qmp-combo: rename DP_PHY register pointer
  phy: qcom-qmp-combo: rename common-register pointers
  phy: qcom-qmp-combo: clean up DP clock callbacks
  phy: qcom-qmp-combo: separate clock and provider registration
  phy: qcom-qmp-combo: add clock registration helper
  ...
parents b8fd76f4 bea3ce75

Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml

+11 −0
Original line number Diff line number Diff line
@@ -17,13 +17,20 @@ properties: 
  compatible:

    oneOf:

      - const: allwinner,sun6i-a31-mipi-dphy

      - const: allwinner,sun50i-a100-mipi-dphy

      - items:

          - const: allwinner,sun50i-a64-mipi-dphy

          - const: allwinner,sun6i-a31-mipi-dphy

      - items:

          - const: allwinner,sun20i-d1-mipi-dphy

          - const: allwinner,sun50i-a100-mipi-dphy



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: Bus Clock
@@ -53,6 +60,7 @@ required: 
  - "#phy-cells"

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - resets
@@ -61,9 +69,12 @@ additionalProperties: false 


examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    dphy0: d-phy@1ca1000 {

        compatible = "allwinner,sun6i-a31-mipi-dphy";

        reg = <0x01ca1000 0x1000>;

        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&ccu 23>, <&ccu 97>;

        clock-names = "bus", "mod";

        resets = <&ccu 4>;

Documentation/devicetree/bindings/phy/allwinner,sun8i-h3-usb-phy.yaml

+26 −0
Original line number Diff line number Diff line
@@ -36,18 +36,22 @@ properties: 
      - const: pmu3



  clocks:

    minItems: 4

    items:

      - description: USB OTG PHY bus clock

      - description: USB Host 0 PHY bus clock

      - description: USB Host 1 PHY bus clock

      - description: USB Host 2 PHY bus clock

      - description: PMU clock for host port 2



  clock-names:

    minItems: 4

    items:

      - const: usb0_phy

      - const: usb1_phy

      - const: usb2_phy

      - const: usb3_phy

      - const: pmu2_clk



  resets:

    items:
@@ -96,6 +100,28 @@ required: 
  - resets

  - reset-names



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - allwinner,sun50i-h616-usb-phy

    then:

      properties:

        clocks:

          minItems: 5



        clock-names:

          minItems: 5

    else:

      properties:

        clocks:

          maxItems: 4



        clock-names:

          maxItems: 4



additionalProperties: false



examples:

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml

+13 −3
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ properties: 
  compatible:

    enum:

      - fsl,imx8mm-pcie-phy

      - fsl,imx8mp-pcie-phy



  reg:

    maxItems: 1
@@ -28,11 +29,16 @@ properties: 
      - const: ref



  resets:

    maxItems: 1

    minItems: 1

    maxItems: 2



  reset-names:

    items:

    oneOf:

      - items:          # for iMX8MM

          - const: pciephy

      - items:          # for IMX8MP

          - const: pciephy

          - const: perst



  fsl,refclk-pad-mode:

    description: |
@@ -60,6 +66,10 @@ properties: 
    description: A boolean property indicating the CLKREQ# signal is

      not supported in the board design (optional)



  power-domains:

    description: PCIe PHY  power domain (optional).

    maxItems: 1



required:

  - "#phy-cells"

  - compatible

Documentation/devicetree/bindings/phy/qcom,qmp-pcie-phy.yaml→Documentation/devicetree/bindings/phy/qcom,ipq8074-qmp-pcie-phy.yaml

+5 −2
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/qcom,qmp-pcie-phy.yaml#

$id: http://devicetree.org/schemas/phy/qcom,ipq8074-qmp-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm QMP PHY controller (PCIe)

title: Qualcomm QMP PHY controller (PCIe, IPQ8074)



maintainers:

  - Vinod Koul <vkoul@kernel.org>
@@ -13,6 +13,9 @@ description: 
  QMP PHY controller supports physical layer functionality for a number of

  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.



  Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see

  qcom,sc8280xp-qmp-pcie-phy.yaml.



properties:

  compatible:

    enum:

Documentation/devicetree/bindings/phy/qcom,qmp-ufs-phy.yaml→Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml

+9 −8
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/qcom,qmp-ufs-phy.yaml#

$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-ufs-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm QMP PHY controller (UFS)

title: Qualcomm QMP PHY controller (UFS, MSM8996)



maintainers:

  - Vinod Koul <vkoul@kernel.org>
@@ -13,13 +13,15 @@ description: 
  QMP PHY controller supports physical layer functionality for a number of

  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.



  Note that these bindings are for SoCs up to SC8180X. For newer SoCs, see

  qcom,sc8280xp-qmp-ufs-phy.yaml.



properties:

  compatible:

    enum:

      - qcom,msm8996-qmp-ufs-phy

      - qcom,msm8998-qmp-ufs-phy

      - qcom,sc8180x-qmp-ufs-phy

      - qcom,sc8280xp-qmp-ufs-phy

      - qcom,sdm845-qmp-ufs-phy

      - qcom,sm6115-qmp-ufs-phy

      - qcom,sm6350-qmp-ufs-phy
@@ -119,7 +121,6 @@ allOf: 
            enum:

              - qcom,msm8998-qmp-ufs-phy

              - qcom,sc8180x-qmp-ufs-phy

              - qcom,sc8280xp-qmp-ufs-phy

              - qcom,sdm845-qmp-ufs-phy

              - qcom,sm6115-qmp-ufs-phy

              - qcom,sm6350-qmp-ufs-phy
@@ -156,7 +157,6 @@ allOf: 
          contains:

            enum:

              - qcom,msm8998-qmp-ufs-phy

              - qcom,sc8280xp-qmp-ufs-phy

              - qcom,sdm845-qmp-ufs-phy

              - qcom,sm6350-qmp-ufs-phy

              - qcom,sm8150-qmp-ufs-phy
@@ -211,11 +211,12 @@ allOf: 


examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>

    #include <dt-bindings/clock/qcom,gcc-sm8250.h>

    #include <dt-bindings/clock/qcom,rpmh.h>



    phy-wrapper@1d87000 {

        compatible = "qcom,sc8280xp-qmp-ufs-phy";

        reg = <0x01d87000 0xe10>;

        compatible = "qcom,sm8250-qmp-ufs-phy";

        reg = <0x01d87000 0x1c0>;

        #address-cells = <1>;

        #size-cells = <1>;

        ranges = <0x0 0x01d87000 0x1000>;