Commit e762bdf5 authored by Matthew Auld's avatar Matthew Auld Committed by Daniel Vetter
Browse files

drm/i915/gtt/dg1: add PTE_LM plumbing for GGTT 



For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.

Based on a patch from Michel Thierry.

BSpec: 45015

Signed-off-by: default avatarMatthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20210203171231.551338-3-matthew.auld@intel.com


Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 11724eea

drivers/gpu/drm/i915/gt/intel_ggtt.c

+19 −5
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ 


#include <drm/i915_drm.h>



#include "gem/i915_gem_lmem.h"



#include "intel_gt.h"

#include "i915_drv.h"

#include "i915_scatterlist.h"
@@ -189,7 +191,12 @@ static u64 gen8_ggtt_pte_encode(dma_addr_t addr, 
				enum i915_cache_level level,

				u32 flags)

{

	return addr | _PAGE_PRESENT;

	gen8_pte_t pte = addr | _PAGE_PRESENT;



	if (flags & PTE_LM)

		pte |= GEN12_GGTT_PTE_LM;



	return pte;

}



static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
@@ -201,13 +208,13 @@ static void gen8_ggtt_insert_page(struct i915_address_space *vm, 
				  dma_addr_t addr,

				  u64 offset,

				  enum i915_cache_level level,

				  u32 unused)

				  u32 flags)

{

	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);

	gen8_pte_t __iomem *pte =

		(gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;



	gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));

	gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, flags));



	ggtt->invalidate(ggtt);

}
@@ -217,7 +224,7 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm, 
				     enum i915_cache_level level,

				     u32 flags)

{

	const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0);

	const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, flags);

	struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);

	gen8_pte_t __iomem *gte;

	gen8_pte_t __iomem *end;
@@ -459,6 +466,8 @@ static void ggtt_bind_vma(struct i915_address_space *vm, 
	pte_flags = 0;

	if (i915_gem_object_is_readonly(obj))

		pte_flags |= PTE_READ_ONLY;

	if (i915_gem_object_is_lmem(obj))

		pte_flags |= PTE_LM;



	vm->insert_entries(vm, vma, cache_level, pte_flags);

	vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
@@ -794,6 +803,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) 
	struct drm_i915_private *i915 = ggtt->vm.i915;

	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);

	phys_addr_t phys_addr;

	u32 pte_flags;

	int ret;



	/* For Modern GENs the PTEs and register space are split in the BAR */
@@ -823,9 +833,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) 
		return ret;

	}



	pte_flags = 0;

	if (i915_gem_object_is_lmem(ggtt->vm.scratch[0]))

		pte_flags |= PTE_LM;



	ggtt->vm.scratch[0]->encode =

		ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),

				    I915_CACHE_NONE, 0);

				    I915_CACHE_NONE, pte_flags);



	return 0;

}

drivers/gpu/drm/i915/gt/intel_gtt.h

+3 −1
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ typedef u64 gen8_pte_t; 


#define GEN12_PPGTT_PTE_LM	BIT_ULL(11)



#define GEN12_GGTT_PTE_LM	BIT_ULL(1)



/*

 * Cacheability Control is a 4-bit value. The low three bits are stored in bits

 * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.