Commit e75a58db authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'phy-for-5.17' of... 

Merge tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

Vinod writes:

phy-for-5.17

  - New support:
        - Qualcomm eDP PHY driver
	- Qualcomm SM8450 UFS, USB2, USB3, PCIe0 and PCIe1 phy support
	- Lan966x ethernet serdes PHY driver
	- Support for uniphier NXI & Pro4 SoC
        - Qualcomm SM6350 USB2 support
	- Amlogic Meson8 HDMI TX PHY driver
	- Rockchip rk3568 usb2 support
	- Intel Thunder Bay eMMC PHY driver
	- Freescale IMX8 PCIe phy driver

  - Updates:
	- Cadence Sierra driver updates for multilink configurations
        - Bcm usb2 updates for Phy reg space

* tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits)
  phy: cadence: Sierra: Add support for derived reference clock output
  dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock
  phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
  phy: cadence: Sierra: Add support for PHY multilink configurations
  phy: cadence: Sierra: Fix to get correct parent for mux clocks
  phy: cadence: Sierra: Update single link PCIe register configuration
  phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
  phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
  phy: cadence: Sierra: Add PHY PCS common register configurations
  phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation
  phy: cadence: Sierra: Add support to get SSC type from device tree
  dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
  dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names
  phy: cadence: Sierra: Prepare driver to add support for multilink configurations
  phy: cadence: Sierra: Use of_device_get_match_data() to get driver data
  phy: mediatek: Fix missing check in mtk_mipi_tx_probe
  phy: uniphier-usb3ss: fix unintended writing zeros to PHY register
  phy: phy-mtk-tphy: use new io helpers to access register
  phy: phy-mtk-xsphy: use new io helpers to access register
  phy: mediatek: add helpers to update bits of registers
  ...
parents 1563fca2 09d976b3

Documentation/devicetree/bindings/phy/amlogic,meson8-hdmi-tx-phy.yaml

0 → 100644
+65 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/amlogic,meson8-hdmi-tx-phy.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Amlogic Meson8, Meson8b and Meson8m2 HDMI TX PHY



maintainers:

  - Martin Blumenstingl <martin.blumenstingl@googlemail.com>



description: |+

  The HDMI TX PHY node should be the child of a syscon node with the

  required property:



  compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"



  Refer to the bindings described in

  Documentation/devicetree/bindings/mfd/syscon.yaml



properties:

  $nodename:

    pattern: "^hdmi-phy@[0-9a-f]+$"



  compatible:

    oneOf:

      - items:

          - enum:

              - amlogic,meson8b-hdmi-tx-phy

              - amlogic,meson8m2-hdmi-tx-phy

          - const: amlogic,meson8-hdmi-tx-phy

      - const: amlogic,meson8-hdmi-tx-phy



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    description:

      HDMI TMDS clock



  "#phy-cells":

    const: 0



required:

  - compatible

  - "#phy-cells"



additionalProperties: false



examples:

  - |

    hdmi-phy@3a0 {

      compatible = "amlogic,meson8-hdmi-tx-phy";

      reg = <0x3a0 0xc>;

      clocks = <&tmds_clock>;

      #phy-cells = <0>;

    };

  - |

    hdmi-phy@3a0 {

      compatible = "amlogic,meson8b-hdmi-tx-phy", "amlogic,meson8-hdmi-tx-phy";

      reg = <0x3a0 0xc>;

      clocks = <&tmds_clock>;

      #phy-cells = <0>;

    };

Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml

0 → 100644
+92 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings



maintainers:

  - Richard Zhu <hongxing.zhu@nxp.com>



properties:

  "#phy-cells":

    const: 0



  compatible:

    enum:

      - fsl,imx8mm-pcie-phy



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: ref



  resets:

    maxItems: 1



  reset-names:

    items:

      - const: pciephy



  fsl,refclk-pad-mode:

    description: |

      Specifies the mode of the refclk pad used. It can be UNUSED(PHY

      refclock is derived from SoC internal source), INPUT(PHY refclock

      is provided externally via the refclk pad) or OUTPUT(PHY refclock

      is derived from SoC internal source and provided on the refclk pad).

      Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants

      to be used.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 0, 1, 2 ]



  fsl,tx-deemph-gen1:

    description: Gen1 De-emphasis value (optional).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,tx-deemph-gen2:

    description: Gen2 De-emphasis value (optional).

    $ref: /schemas/types.yaml#/definitions/uint32

    default: 0



  fsl,clkreq-unsupported:

    type: boolean

    description: A boolean property indicating the CLKREQ# signal is

      not supported in the board design (optional)



required:

  - "#phy-cells"

  - compatible

  - reg

  - clocks

  - clock-names

  - fsl,refclk-pad-mode



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/imx8mm-clock.h>

    #include <dt-bindings/phy/phy-imx8-pcie.h>

    #include <dt-bindings/reset/imx8mq-reset.h>



    pcie_phy: pcie-phy@32f00000 {

            compatible = "fsl,imx8mm-pcie-phy";

            reg = <0x32f00000 0x10000>;

            clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;

            clock-names = "ref";

            assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;

            assigned-clock-rates = <100000000>;

            assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;

            resets = <&src IMX8MQ_RESET_PCIEPHY>;

            reset-names = "pciephy";

            fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;

            #phy-cells = <0>;

    };

...

Documentation/devicetree/bindings/phy/intel,phy-thunderbay-emmc.yaml

0 → 100644
+46 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/intel,phy-thunderbay-emmc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Intel Thunder Bay eMMC PHY bindings



maintainers:

  - Srikandan Nandhini <nandhini.srikandan@intel.com>



properties:

  compatible:

    const: intel,thunderbay-emmc-phy



  "#phy-cells":

    const: 0



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    items:

      - const: emmcclk



required:

  - "#phy-cells"

  - compatible

  - reg

  - clocks



additionalProperties: false



examples:

  - |

     mmc_phy@80440800 {

     #phy-cells = <0x0>;

     compatible = "intel,thunderbay-emmc-phy";

     status = "okay";

     reg = <0x80440800 0x100>;

     clocks = <&emmc>;

     clock-names = "emmcclk";

     };

Documentation/devicetree/bindings/phy/mediatek,tphy.yaml

+18 −0
Original line number Diff line number Diff line
@@ -160,6 +160,24 @@ patternProperties: 
                - PHY_TYPE_PCIE

                - PHY_TYPE_SATA



      nvmem-cells:

        items:

          - description: internal R efuse for U2 PHY or U3/PCIe PHY

          - description: rx_imp_sel efuse for U3/PCIe PHY

          - description: tx_imp_sel efuse for U3/PCIe PHY

        description: |

          Phandles to nvmem cell that contains the efuse data;

          Available only for U2 PHY or U3/PCIe PHY of version 2/3, these

          three items should be provided at the same time for U3/PCIe PHY,

          when use software to load efuse;

          If unspecified, will use hardware auto-load efuse.



      nvmem-cell-names:

        items:

          - const: intr

          - const: rx_imp

          - const: tx_imp



      # The following optional vendor properties are only for debug or HQA test

      mediatek,eye-src:

        description:

Documentation/devicetree/bindings/phy/microchip,lan966x-serdes.yaml

0 → 100644
+59 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip Lan966x Serdes controller



maintainers:

  - Horatiu Vultur <horatiu.vultur@microchip.com>



description: |

  Lan966x has 7 interfaces, consisting of 2 copper transceivers(CU),

  3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII.

  Also it has 8 logical Ethernet ports which can be connected to these

  interfaces. The Serdes controller will allow to configure these interfaces

  and allows to "mux" the interfaces to different ports.



  For simple selection of the interface that is used with a port, the

  following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a

  number that represents the index of that interface type. For example

  CU(1) means use interface copper transceivers 1. SERDES6G(2) means use

  interface SerDes 2.



properties:

  $nodename:

    pattern: "^serdes@[0-9a-f]+$"



  compatible:

    const: microchip,lan966x-serdes



  reg:

    items:

      - description: HSIO registers

      - description: HW_STAT register



  '#phy-cells':

    const: 2

    description: |

      - Input port to use for a given macro.

      - The macro to be used. The macros are defined in

        dt-bindings/phy/phy-lan966x-serdes.



required:

  - compatible

  - reg

  - '#phy-cells'



additionalProperties: false



examples:

  - |

    serdes: serdes@e2004010 {

      compatible = "microchip,lan966x-serdes";

      reg = <0xe202c000 0x9c>, <0xe2004010 0x4>;

      #phy-cells = <2>;

    };



...