Commit e74c8a46 authored by Joshua Aberback's avatar Joshua Aberback Committed by Alex Deucher
Browse files

drm/amd/display: Update idle optimization handling 



[How]
 - use dc interface instead of hwss interface in cursor functions, to keep
dc->idle_optimizations_allowed updated
 - add dc interface to check if idle optimizations might apply to a plane

Signed-off-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f01afd1e

drivers/gpu/drm/amd/display/dc/core/dc.c

+4 −2
Original line number Diff line number Diff line
@@ -3138,9 +3138,11 @@ void dc_lock_memory_clock_frequency(struct dc *dc) 
			core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);

}



bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc,

						 struct dc_plane_state *plane)

bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc, struct dc_plane_state *plane)

{

	if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane))

		return true;



	return false;

}

drivers/gpu/drm/amd/display/dc/dc.h

+4 −0
Original line number Diff line number Diff line
@@ -171,6 +171,9 @@ struct dc_caps { 
	bool dmcub_support;

	uint32_t num_of_internal_disp;

	enum dp_protocol_version max_dp_protocol_version;

	unsigned int mall_size_per_mem_channel;

	unsigned int mall_size_total;

	unsigned int cursor_cache_size;

	struct dc_plane_cap planes[MAX_PLANES];

	struct dc_color_caps color;

};
@@ -499,6 +502,7 @@ struct dc_debug_options { 
	bool dmcub_emulation;

#if defined(CONFIG_DRM_AMD_DC_DCN)

	bool disable_idle_power_optimizations;

	unsigned int mall_size_override;

#endif

	bool dmub_command_table; /* for testing only */

	struct dc_bw_validation_profile bw_val_profile;

drivers/gpu/drm/amd/display/dc/dc_hw_types.h

+1 −0
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ struct dc_plane_address { 
	union {

		struct{

			PHYSICAL_ADDRESS_LOC addr;

			PHYSICAL_ADDRESS_LOC cursor_cache_addr;

			PHYSICAL_ADDRESS_LOC meta_addr;

			union large_integer dcc_const_color;

		} grph;

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c

+13 −0
Original line number Diff line number Diff line
@@ -814,6 +814,19 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable) 
	return true;

}



bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane)

{

	// add meta size?

	unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *

			(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);

	unsigned int mall_size = dc->caps.mall_size_total;



	if (dc->debug.mall_size_override)

		mall_size = 1024 * 1024 * dc->debug.mall_size_override;



	return (surface_size + dc->caps.cursor_cache_size) < mall_size;

}



void dcn30_hardware_release(struct dc *dc)

{

	/* if pstate unsupported, force it supported */

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h

+2 −0
Original line number Diff line number Diff line
@@ -65,6 +65,8 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 
void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);

void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);



bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane);



bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);



void dcn30_hardware_release(struct dc *dc);