Commit e749ef96 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo
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wifi: rtw89: add counters of register-based H2C/C2H



The register-based H2C/C2H are used to exchange information between driver
and firmware, but only apply to narrow area because its data size is
smaller than regular packet-based H2C/C2H.

This kind of H2C/C2H must be paired. To identify if any H2C/C2H is missing,
update counters to help diagnose this kind of problems.

Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20230316063956.71687-1-pkshih@realtek.com
parent 7527251f
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+4 −0
Original line number Diff line number Diff line
@@ -3140,8 +3140,10 @@ struct rtw89_chip_info {
	u32 txwd_body_size;
	u32 h2c_ctrl_reg;
	const u32 *h2c_regs;
	struct rtw89_reg_def h2c_counter_reg;
	u32 c2h_ctrl_reg;
	const u32 *c2h_regs;
	struct rtw89_reg_def c2h_counter_reg;
	const struct rtw89_page_regs *page_regs;
	bool cfo_src_fd;
	const struct rtw89_reg_def *dcfo_comp;
@@ -3268,6 +3270,8 @@ struct rtw89_fw_info {
	struct completion completion;
	u8 h2c_seq;
	u8 rec_seq;
	u8 h2c_counter;
	u8 c2h_counter;
	struct rtw89_fw_suit normal;
	struct rtw89_fw_suit wowlan;
	bool fw_log_enable;
+11 −0
Original line number Diff line number Diff line
@@ -615,6 +615,8 @@ int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type)

	fw_info->h2c_seq = 0;
	fw_info->rec_seq = 0;
	fw_info->h2c_counter = 0;
	fw_info->c2h_counter = 0;
	rtwdev->mac.rpwm_seq_num = RPWM_SEQ_NUM_MAX;
	rtwdev->mac.cpwm_seq_num = CPWM_SEQ_NUM_MAX;

@@ -2724,6 +2726,7 @@ static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,
				  struct rtw89_mac_h2c_info *info)
{
	const struct rtw89_chip_info *chip = rtwdev->chip;
	struct rtw89_fw_info *fw_info = &rtwdev->fw;
	const u32 *h2c_reg = chip->h2c_regs;
	u8 i, val, len;
	int ret;
@@ -2743,6 +2746,9 @@ static int rtw89_fw_write_h2c_reg(struct rtw89_dev *rtwdev,
	for (i = 0; i < RTW89_H2CREG_MAX; i++)
		rtw89_write32(rtwdev, h2c_reg[i], info->h2creg[i]);

	fw_info->h2c_counter++;
	rtw89_write8_mask(rtwdev, chip->h2c_counter_reg.addr,
			  chip->h2c_counter_reg.mask, fw_info->h2c_counter);
	rtw89_write8(rtwdev, chip->h2c_ctrl_reg, B_AX_H2CREG_TRIGGER);

	return 0;
@@ -2752,6 +2758,7 @@ static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev,
				 struct rtw89_mac_c2h_info *info)
{
	const struct rtw89_chip_info *chip = rtwdev->chip;
	struct rtw89_fw_info *fw_info = &rtwdev->fw;
	const u32 *c2h_reg = chip->c2h_regs;
	u32 ret;
	u8 i, val;
@@ -2775,6 +2782,10 @@ static int rtw89_fw_read_c2h_reg(struct rtw89_dev *rtwdev,
	info->content_len = (RTW89_GET_C2H_HDR_LEN(*info->c2hreg) << 2) -
				RTW89_C2HREG_HDR_LEN;

	fw_info->c2h_counter++;
	rtw89_write8_mask(rtwdev, chip->c2h_counter_reg.addr,
			  chip->c2h_counter_reg.mask, fw_info->c2h_counter);

	return 0;
}

+2 −0
Original line number Diff line number Diff line
@@ -3398,6 +3398,8 @@ int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
	if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
		return -EFAULT;

	rtw89_write32(rtwdev, R_AX_UDM1, 0);
	rtw89_write32(rtwdev, R_AX_UDM2, 0);
	rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
	rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
	rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
+5 −0
Original line number Diff line number Diff line
@@ -207,6 +207,11 @@

#define R_AX_UDM0 0x01F0
#define R_AX_UDM1 0x01F4
#define B_AX_UDM1_MASK GENMASK(31, 16)
#define B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK GENMASK(15, 12)
#define B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK GENMASK(11, 8)
#define B_AX_UDM1_WCPU_C2H_ENQ_CNT_MASK GENMASK(7, 4)
#define B_AX_UDM1_WCPU_H2C_DEQ_CNT_MASK GENMASK(3, 0)
#define R_AX_UDM2 0x01F8
#define R_AX_UDM3 0x01FC

+2 −0
Original line number Diff line number Diff line
@@ -2136,9 +2136,11 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
	.h2c_desc_size		= sizeof(struct rtw89_txwd_body),
	.txwd_body_size		= sizeof(struct rtw89_txwd_body),
	.h2c_ctrl_reg		= R_AX_H2CREG_CTRL,
	.h2c_counter_reg	= {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8},
	.h2c_regs		= rtw8852a_h2c_regs,
	.c2h_ctrl_reg		= R_AX_C2HREG_CTRL,
	.c2h_regs		= rtw8852a_c2h_regs,
	.c2h_counter_reg	= {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8},
	.page_regs		= &rtw8852a_page_regs,
	.cfo_src_fd		= false,
	.dcfo_comp		= &rtw8852a_dcfo_comp,
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