Commit e7241670 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.4-tag1' of... 

Merge tag 'renesas-clk-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel
   Selector (ISPCS), and video capture (VIN) clocks on R-Car V4H
 - Add video capture (VIN) clocks on R-Car V3H
 - Add Cortex-A53 System CPU (Z2) clocks on R-Car V3M and V3H
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: Convert to platform remove callback returning void
  clk: renesas: r9a06g032: Improve clock tables
  clk: renesas: r9a06g032: Document structs
  clk: renesas: r9a06g032: Drop unused fields
  clk: renesas: r9a06g032: Improve readability
  clk: renesas: r8a77980: Add Z2 clock
  clk: renesas: r8a77970: Add Z2 clock
  clk: renesas: r8a77995: Fix VIN parent clock
  clk: renesas: r8a77980: Add VIN clocks
  clk: renesas: r8a779g0: Add VIN clocks
  clk: renesas: r8a779g0: Add ISPCS clocks
  clk: renesas: r8a779g0: Add CSI-2 clocks
  clk: renesas: r8a779g0: Add thermal clock
  clk: renesas: r8a779g0: Add Audio clocks
  clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
parents fe15c26e 72cd8436

drivers/clk/renesas/r8a77970-cpg-mssr.c

+1 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] __initconst = { 
	DEF_FIXED(".pll1_div4",	CLK_PLL1_DIV4,	CLK_PLL1_DIV2,	2, 1),



	/* Core Clock Outputs */

	DEF_FIXED("z2",		R8A77970_CLK_Z2,    CLK_PLL1_DIV4,  1, 1),

	DEF_FIXED("ztr",	R8A77970_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",	R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",		R8A77970_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

drivers/clk/renesas/r8a77980-cpg-mssr.c

+17 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] __initconst = { 
	DEF_RATE(".oco",	CLK_OCO,           32768),



	/* Core Clock Outputs */

	DEF_FIXED("z2",		R8A77980_CLK_Z2,    CLK_PLL2,       4, 1),

	DEF_FIXED("ztr",	R8A77980_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",	R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",		R8A77980_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),
@@ -150,11 +151,27 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = { 
	DEF_MOD("imp-ocv3",		 529,	R8A77980_CLK_S1D1),

	DEF_MOD("imp-ocv2",		 531,	R8A77980_CLK_S1D1),

	DEF_MOD("fcpvd0",		 603,	R8A77980_CLK_S3D1),

	DEF_MOD("vin15",		 604,	R8A77980_CLK_S2D1),

	DEF_MOD("vin14",		 605,	R8A77980_CLK_S2D1),

	DEF_MOD("vin13",		 608,	R8A77980_CLK_S2D1),

	DEF_MOD("vin12",		 612,	R8A77980_CLK_S2D1),

	DEF_MOD("vin11",		 618,	R8A77980_CLK_S2D1),

	DEF_MOD("vspd0",		 623,	R8A77980_CLK_S3D1),

	DEF_MOD("vin10",		 625,	R8A77980_CLK_S2D1),

	DEF_MOD("vin9",			 627,	R8A77980_CLK_S2D1),

	DEF_MOD("vin8",			 628,	R8A77980_CLK_S2D1),

	DEF_MOD("csi41",		 715,	R8A77980_CLK_CSI0),

	DEF_MOD("csi40",		 716,	R8A77980_CLK_CSI0),

	DEF_MOD("du0",			 724,	R8A77980_CLK_S2D1),

	DEF_MOD("lvds",			 727,	R8A77980_CLK_S2D1),

	DEF_MOD("vin7",			 804,	R8A77980_CLK_S2D1),

	DEF_MOD("vin6",			 805,	R8A77980_CLK_S2D1),

	DEF_MOD("vin5",			 806,	R8A77980_CLK_S2D1),

	DEF_MOD("vin4",			 807,	R8A77980_CLK_S2D1),

	DEF_MOD("vin3",			 808,	R8A77980_CLK_S2D1),

	DEF_MOD("vin2",			 809,	R8A77980_CLK_S2D1),

	DEF_MOD("vin1",			 810,	R8A77980_CLK_S2D1),

	DEF_MOD("vin0",			 811,	R8A77980_CLK_S2D1),

	DEF_MOD("etheravb",		 812,	R8A77980_CLK_S3D2),

	DEF_MOD("gether",		 813,	R8A77980_CLK_S3D2),

	DEF_MOD("imp3",			 824,	R8A77980_CLK_S1D1),

drivers/clk/renesas/r8a77995-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = { 
	DEF_MOD("du0",			 724,	R8A77995_CLK_S1D1),

	DEF_MOD("lvds",			 727,	R8A77995_CLK_S2D1),

	DEF_MOD("mlp",			 802,	R8A77995_CLK_S2D1),

	DEF_MOD("vin4",			 807,	R8A77995_CLK_S1D2),

	DEF_MOD("vin4",			 807,	R8A77995_CLK_S3D1),

	DEF_MOD("etheravb",		 812,	R8A77995_CLK_S3D2),

	DEF_MOD("imr0",			 823,	R8A77995_CLK_S1D2),

	DEF_MOD("gpio6",		 906,	R8A77995_CLK_S3D4),

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+24 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("vcbus",	R8A779G0_CLK_VCBUS,	CLK_VC,		1, 1),

	DEF_FIXED("vcbusd2",	R8A779G0_CLK_VCBUSD2,	CLK_VC,		2, 1),

	DEF_DIV6P1("canfd",     R8A779G0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),

	DEF_DIV6P1("csi",	R8A779G0_CLK_CSI,	CLK_PLL5_DIV4,	0x880),

	DEF_FIXED("dsiref",	R8A779G0_CLK_DSIREF,	CLK_PLL5_DIV4,	48, 1),

	DEF_DIV6P1("dsiext",	R8A779G0_CLK_DSIEXT,	CLK_PLL5_DIV4,	0x884),
@@ -165,6 +166,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("canfd0",	328,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("csi40",	331,	R8A779G0_CLK_CSI),

	DEF_MOD("csi41",	400,	R8A779G0_CLK_CSI),

	DEF_MOD("dis0",		411,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("dsitxlink0",	415,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("dsitxlink1",	416,	R8A779G0_CLK_VIOBUSD2),
@@ -181,6 +184,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("i2c4",		522,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("i2c5",		523,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("irqc",		611,	R8A779G0_CLK_CL16M),

	DEF_MOD("ispcs0",	612,	R8A779G0_CLK_S0D2_VIO),

	DEF_MOD("ispcs1",	613,	R8A779G0_CLK_S0D2_VIO),

	DEF_MOD("msi0",		618,	R8A779G0_CLK_MSO),

	DEF_MOD("msi1",		619,	R8A779G0_CLK_MSO),

	DEF_MOD("msi2",		620,	R8A779G0_CLK_MSO),
@@ -202,6 +207,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("tmu3",		716,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tmu4",		717,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tpu0",		718,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("vin00",	730,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin01",	731,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin02",	800,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin03",	801,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin04",	802,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin05",	803,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin06",	804,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin07",	805,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin10",	806,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin11",	807,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin12",	808,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin13",	809,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin14",	810,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin15",	811,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin16",	812,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vin17",	813,	R8A779G0_CLK_S0D4_VIO),

	DEF_MOD("vspd0",	830,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("vspd1",	831,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("wdt1:wdt0",	907,	R8A779G0_CLK_R),
@@ -213,6 +234,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("pfc1",		916,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc2",		917,	R8A779G0_CLK_CL16M),

	DEF_MOD("pfc3",		918,	R8A779G0_CLK_CL16M),

	DEF_MOD("tsc",		919,	R8A779G0_CLK_CL16M),

	DEF_MOD("ssiu",		2926,	R8A779G0_CLK_S0D6_PER),

	DEF_MOD("ssi",		2927,	R8A779G0_CLK_S0D6_PER),

};



/*

drivers/clk/renesas/r9a06g032-clocks.c

+541 −195

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