Commit e6f19648 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915: move fbc_mask to runtime info 



If it's modified runtime, it's runtime info.

v2: Rebase on mtl fbc_mask

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMaarten Lankhort <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/dd1898084b732ba265b212ddbc0fcdd826c11820.1660910433.git.jani.nikula@intel.com
parent 43ba44a1

drivers/gpu/drm/i915/display/intel_fbc.c

+3 −3
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ 


#define for_each_fbc_id(__dev_priv, __fbc_id) \

	for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \

		for_each_if(INTEL_INFO(__dev_priv)->display.fbc_mask & BIT(__fbc_id))

		for_each_if(RUNTIME_INFO(__dev_priv)->fbc_mask & BIT(__fbc_id))



#define for_each_intel_fbc(__dev_priv, __fbc, __fbc_id) \

	for_each_fbc_id((__dev_priv), (__fbc_id)) \
@@ -1710,10 +1710,10 @@ void intel_fbc_init(struct drm_i915_private *i915) 
	enum intel_fbc_id fbc_id;



	if (!drm_mm_initialized(&i915->mm.stolen))

		mkwrite_device_info(i915)->display.fbc_mask = 0;

		RUNTIME_INFO(i915)->fbc_mask = 0;



	if (need_fbc_vtd_wa(i915))

		mkwrite_device_info(i915)->display.fbc_mask = 0;

		RUNTIME_INFO(i915)->fbc_mask = 0;



	i915->params.enable_fbc = intel_sanitize_fbc_option(i915);

	drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n",

drivers/gpu/drm/i915/display/skl_universal_plane.c

+1 −1
Original line number Diff line number Diff line
@@ -1929,7 +1929,7 @@ static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) 
static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,

			      enum intel_fbc_id fbc_id, enum plane_id plane_id)

{

	if ((INTEL_INFO(dev_priv)->display.fbc_mask & BIT(fbc_id)) == 0)

	if ((RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)

		return false;



	return plane_id == PLANE_PRIMARY;

drivers/gpu/drm/i915/i915_drv.h

+1 −1
Original line number Diff line number Diff line
@@ -1249,7 +1249,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, 
#define I915_HAS_HOTPLUG(dev_priv)	(INTEL_INFO(dev_priv)->display.has_hotplug)



#define HAS_FW_BLC(dev_priv)	(DISPLAY_VER(dev_priv) > 2)

#define HAS_FBC(dev_priv)	(INTEL_INFO(dev_priv)->display.fbc_mask != 0)

#define HAS_FBC(dev_priv)	(RUNTIME_INFO(dev_priv)->fbc_mask != 0)

#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)



#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))

drivers/gpu/drm/i915/i915_pci.c

+12 −12
Original line number Diff line number Diff line
@@ -222,13 +222,13 @@ static const struct intel_device_info i845g_info = { 
static const struct intel_device_info i85x_info = {

	I830_FEATURES,

	PLATFORM(INTEL_I85X),

	.display.fbc_mask = BIT(INTEL_FBC_A),

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),

};



static const struct intel_device_info i865g_info = {

	I845_FEATURES,

	PLATFORM(INTEL_I865G),

	.display.fbc_mask = BIT(INTEL_FBC_A),

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),

};



#define GEN3_FEATURES \
@@ -267,7 +267,7 @@ static const struct intel_device_info i915gm_info = { 
	.display.has_overlay = 1,

	.display.overlay_needs_physical = 1,

	.display.supports_tv = 1,

	.display.fbc_mask = BIT(INTEL_FBC_A),

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),

	.hws_needs_physical = 1,

	.unfenced_needs_alignment = 1,

};
@@ -292,7 +292,7 @@ static const struct intel_device_info i945gm_info = { 
	.display.has_overlay = 1,

	.display.overlay_needs_physical = 1,

	.display.supports_tv = 1,

	.display.fbc_mask = BIT(INTEL_FBC_A),

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),

	.hws_needs_physical = 1,

	.unfenced_needs_alignment = 1,

};
@@ -352,7 +352,7 @@ static const struct intel_device_info i965gm_info = { 
	GEN4_FEATURES,

	PLATFORM(INTEL_I965GM),

	.is_mobile = 1,

	.display.fbc_mask = BIT(INTEL_FBC_A),

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),

	.display.has_overlay = 1,

	.display.supports_tv = 1,

	.hws_needs_physical = 1,
@@ -370,7 +370,7 @@ static const struct intel_device_info gm45_info = { 
	GEN4_FEATURES,

	PLATFORM(INTEL_GM45),

	.is_mobile = 1,

	.display.fbc_mask = BIT(INTEL_FBC_A),

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),

	.display.supports_tv = 1,

	.platform_engine_mask = BIT(RCS0) | BIT(VCS0),

	.gpu_reset_clobbers_display = false,
@@ -404,7 +404,7 @@ static const struct intel_device_info ilk_m_info = { 
	PLATFORM(INTEL_IRONLAKE),

	.is_mobile = 1,

	.has_rps = true,

	.display.fbc_mask = BIT(INTEL_FBC_A),

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),

};



#define GEN6_FEATURES \
@@ -412,7 +412,7 @@ static const struct intel_device_info ilk_m_info = { 
	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \

	.display.has_hotplug = 1, \

	.display.fbc_mask = BIT(INTEL_FBC_A), \

	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \

	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \

	.has_3d_pipeline = 1, \

	.has_coherent_ggtt = true, \
@@ -464,7 +464,7 @@ static const struct intel_device_info snb_m_gt2_info = { 
	.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \

	.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \

	.display.has_hotplug = 1, \

	.display.fbc_mask = BIT(INTEL_FBC_A), \

	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \

	.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \

	.has_3d_pipeline = 1, \

	.has_coherent_ggtt = true, \
@@ -707,7 +707,7 @@ static const struct intel_device_info skl_gt4_info = { 
	.has_64bit_reloc = 1, \

	.display.has_ddi = 1, \

	.display.has_fpga_dbg = 1, \

	.display.fbc_mask = BIT(INTEL_FBC_A), \

	.__runtime.fbc_mask = BIT(INTEL_FBC_A), \

	.display.has_hdcp = 1, \

	.display.has_psr = 1, \

	.display.has_psr_hw_tracking = 1, \
@@ -956,7 +956,7 @@ static const struct intel_device_info adl_s_info = { 
	.display.has_dp_mst = 1,						\

	.display.has_dsb = 1,							\

	.display.has_dsc = 1,							\

	.display.fbc_mask = BIT(INTEL_FBC_A),					\

	.__runtime.fbc_mask = BIT(INTEL_FBC_A),					\

	.display.has_fpga_dbg = 1,						\

	.display.has_hdcp = 1,							\

	.display.has_hotplug = 1,						\
@@ -1112,7 +1112,7 @@ static const struct intel_device_info pvc_info = { 
	XE_LPD_FEATURES,	\

	.display.ver = 14,	\

	.display.has_cdclk_crawl = 1, \

	.display.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)

	.__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)



__maybe_unused

static const struct intel_device_info mtl_info = {

drivers/gpu/drm/i915/intel_device_info.c

+3 −3
Original line number Diff line number Diff line
@@ -363,7 +363,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
				 "Display fused off, disabling\n");

			info->display.pipe_mask = 0;

			info->display.cpu_transcoder_mask = 0;

			info->display.fbc_mask = 0;

			runtime->fbc_mask = 0;

		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {

			drm_info(&dev_priv->drm, "PipeC fused off\n");

			info->display.pipe_mask &= ~BIT(PIPE_C);
@@ -375,7 +375,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {

			info->display.pipe_mask &= ~BIT(PIPE_A);

			info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);

			info->display.fbc_mask &= ~BIT(INTEL_FBC_A);

			runtime->fbc_mask &= ~BIT(INTEL_FBC_A);

		}

		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {

			info->display.pipe_mask &= ~BIT(PIPE_B);
@@ -396,7 +396,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
			info->display.has_hdcp = 0;



		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)

			info->display.fbc_mask = 0;

			runtime->fbc_mask = 0;



		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))

			info->display.has_dmc = 0;