Commit e6ef9b39 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amdgpu: correctly toggle gfx on/off around RLC_SPM_* register access 



As part of the ib padding process, accessing the RLC_SPM_* register may
trigger gfx hang. Since gfxoff may be already kicked during the whole period.
To address that, we manually toggle gfx on/off around the RLC_SPM_*
register access.

This can resolve the gfx hang issue observed on running Talos with RDP launched
in parallel.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Acked-by: default avatarGuchun Chen <guchun.chen@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7513c9ff

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+5 −0
Original line number Diff line number Diff line
@@ -8249,6 +8249,9 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)

{

	u32 reg, data;



	amdgpu_gfx_off_ctrl(adev, false);



	/* not for *_SOC15 */

	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);

	if (amdgpu_sriov_is_pp_one_vf(adev))
@@ -8263,6 +8266,8 @@ static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);

	else

		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);



	amdgpu_gfx_off_ctrl(adev, true);

}



static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

+4 −0
Original line number Diff line number Diff line
@@ -3575,12 +3575,16 @@ static void gfx_v7_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
{

	u32 data;



	amdgpu_gfx_off_ctrl(adev, false);



	data = RREG32(mmRLC_SPM_VMID);



	data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;

	data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;



	WREG32(mmRLC_SPM_VMID, data);



	amdgpu_gfx_off_ctrl(adev, true);

}



static void gfx_v7_0_enable_cgcg(struct amdgpu_device *adev, bool enable)

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+4 −0
Original line number Diff line number Diff line
@@ -5624,6 +5624,8 @@ static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
{

	u32 data;



	amdgpu_gfx_off_ctrl(adev, false);



	if (amdgpu_sriov_is_pp_one_vf(adev))

		data = RREG32_NO_KIQ(mmRLC_SPM_VMID);

	else
@@ -5636,6 +5638,8 @@ static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
		WREG32_NO_KIQ(mmRLC_SPM_VMID, data);

	else

		WREG32(mmRLC_SPM_VMID, data);



	amdgpu_gfx_off_ctrl(adev, true);

}



static const struct amdgpu_rlc_funcs iceland_rlc_funcs = {

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+4 −0
Original line number Diff line number Diff line
@@ -5104,6 +5104,8 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
{

	u32 reg, data;



	amdgpu_gfx_off_ctrl(adev, false);



	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);

	if (amdgpu_sriov_is_pp_one_vf(adev))

		data = RREG32_NO_KIQ(reg);
@@ -5117,6 +5119,8 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);

	else

		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);



	amdgpu_gfx_off_ctrl(adev, true);

}



static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev,