Commit e6eb5fe9 authored by Helge Deller's avatar Helge Deller
Browse files

parisc: Drop LDCW barrier in CAS code when running UP 



When running an SMP kernel on a single-CPU machine, we can speed up the
CAS code by replacing the LDCW sync barrier with NOP.

Signed-off-by: default avatarHelge Deller <deller@gmx.de>
parent 62217beb

arch/parisc/kernel/syscall.S

+8 −4
Original line number Diff line number Diff line
@@ -641,7 +641,8 @@ cas_action: 
2:	stw	%r24, 0(%r26)

	/* Free lock */

#ifdef CONFIG_SMP

	LDCW	0(%sr2,%r20), %r1			/* Barrier */

98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */

99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)

#endif

	stw	%r20, 0(%sr2,%r20)

#if ENABLE_LWS_DEBUG
@@ -658,7 +659,8 @@ cas_action: 
	/* Error occurred on load or store */

	/* Free lock */

#ifdef CONFIG_SMP

	LDCW	0(%sr2,%r20), %r1			/* Barrier */

98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */

99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)

#endif

	stw	%r20, 0(%sr2,%r20)

#if ENABLE_LWS_DEBUG
@@ -862,7 +864,8 @@ cas2_action: 
cas2_end:

	/* Free lock */

#ifdef CONFIG_SMP

	LDCW	0(%sr2,%r20), %r1			/* Barrier */

98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */

99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)

#endif

	stw	%r20, 0(%sr2,%r20)

	/* Enable interrupts */
@@ -875,7 +878,8 @@ cas2_end: 
	/* Error occurred on load or store */

	/* Free lock */

#ifdef CONFIG_SMP

	LDCW	0(%sr2,%r20), %r1			/* Barrier */

98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */

99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)

#endif

	stw	%r20, 0(%sr2,%r20)

	ssm	PSW_SM_I, %r0