Commit e6a9acc3 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
Browse files

arm64: dts: renesas: r9a07g043: Add OPP table 



Add OPP table for RZ/G2UL SoC.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 22ec8689

arch/arm64/boot/dts/renesas/r9a07g043.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -42,6 +42,33 @@ 
		clock-frequency = <0>;

	};



	cluster0_opp: opp-table-0 {

		compatible = "operating-points-v2";

		opp-shared;



		opp-125000000 {

			opp-hz = /bits/ 64 <125000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

		opp-250000000 {

			opp-hz = /bits/ 64 <250000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

		opp-500000000 {

			opp-hz = /bits/ 64 <500000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

		};

		opp-1000000000 {

			opp-hz = /bits/ 64 <1000000000>;

			opp-microvolt = <1100000>;

			clock-latency-ns = <300000>;

			opp-suspend;

		};

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;
@@ -53,6 +80,7 @@ 
			next-level-cache = <&L3_CA55>;

			enable-method = "psci";

			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;

			operating-points-v2 = <&cluster0_opp>;

		};



		L3_CA55: cache-controller-0 {