Commit e67db9d2 authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Matt Roper
Browse files

drm/i915/xelp: Implement Wa_1606376872 



Wa_1606376872 applies to all Xe_LP IPs except DG1.

Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230307032238.300674-1-gustavo.sousa@intel.com
parent 6e921328

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -480,6 +480,9 @@ 
#define   HDC_FORCE_NON_COHERENT		(1 << 4)

#define   HDC_BARRIER_PERFORMANCE_DISABLE	(1 << 10)



#define COMMON_SLICE_CHICKEN4			_MMIO(0x7300)

#define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)



#define GEN8_HDC_CHICKEN1			_MMIO(0x7304)



#define GEN11_COMMON_SLICE_CHICKEN3		_MMIO(0x7304)

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −1
Original line number Diff line number Diff line
@@ -743,9 +743,13 @@ static void gen12_ctx_workarounds_init(struct intel_engine_cs *engine, 
	       FF_MODE2_GS_TIMER_224,

	       0, false);



	if (!IS_DG1(i915))

	if (!IS_DG1(i915)) {

		/* Wa_1806527549 */

		wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE);



		/* Wa_1606376872 */

		wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC);

	}

}



static void dg1_ctx_workarounds_init(struct intel_engine_cs *engine,