dt-bindings: clock: Add Qcom SM8350 GPUCC bindings

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Graphics Clock & Reset Controller Binding

maintainers:

  - Robert Foss <robert.foss@linaro.org>

description: |

  Qualcomm graphics clock control module which supports the clocks, resets and

  power domains on Qualcomm SoCs.

  See also:

    dt-bindings/clock/qcom,gpucc-sm8350.h

properties:

  compatible:

    enum:

      - qcom,sm8350-gpucc

  clocks:

    items:

      - description: Board XO source

      - description: GPLL0 main branch source

      - description: GPLL0 div branch source

  '#clock-cells':

    const: 1

  '#reset-cells':

    const: 1

  '#power-domain-cells':

    const: 1

  reg:

    maxItems: 1

required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'

additionalProperties: false

examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sm8350.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    soc {

        #address-cells = <2>;

        #size-cells = <2>;

        clock-controller@3d90000 {

            compatible = "qcom,sm8350-gpucc";

            reg = <0 0x03d90000 0 0x9000>;

            clocks = <&rpmhcc RPMH_CXO_CLK>,

                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,

                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

            #clock-cells = <1>;

            #reset-cells = <1>;

            #power-domain-cells = <1>;

        };

    };

...

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */

/*

 * Copyright (c) 2022, The Linux Foundation. All rights reserved.

 */

#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H

#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8350_H

/* GPU_CC clocks */

#define GPU_CC_AHB_CLK			0

#define GPU_CC_CB_CLK			1

#define GPU_CC_CRC_AHB_CLK		2

#define GPU_CC_CX_APB_CLK		3

#define GPU_CC_CX_GMU_CLK		4

#define GPU_CC_CX_QDSS_AT_CLK		5

#define GPU_CC_CX_QDSS_TRIG_CLK		6

#define GPU_CC_CX_QDSS_TSCTR_CLK	7

#define GPU_CC_CX_SNOC_DVM_CLK		8

#define GPU_CC_CXO_AON_CLK		9

#define GPU_CC_CXO_CLK			10

#define GPU_CC_FREQ_MEASURE_CLK		11

#define GPU_CC_GMU_CLK_SRC		12

#define GPU_CC_GX_GMU_CLK		13

#define GPU_CC_GX_QDSS_TSCTR_CLK	14

#define GPU_CC_GX_VSENSE_CLK		15

#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK	16

#define GPU_CC_HUB_AHB_DIV_CLK_SRC	17

#define GPU_CC_HUB_AON_CLK		18

#define GPU_CC_HUB_CLK_SRC		19

#define GPU_CC_HUB_CX_INT_CLK		20

#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC	21

#define GPU_CC_MND1X_0_GFX3D_CLK	22

#define GPU_CC_MND1X_1_GFX3D_CLK	23

#define GPU_CC_PLL0			24

#define GPU_CC_PLL1			25

#define GPU_CC_SLEEP_CLK		26

/* GPU_CC resets */

#define GPUCC_GPU_CC_ACD_BCR		0

#define GPUCC_GPU_CC_CB_BCR		1

#define GPUCC_GPU_CC_CX_BCR		2

#define GPUCC_GPU_CC_FAST_HUB_BCR	3

#define GPUCC_GPU_CC_GFX3D_AON_BCR	4

#define GPUCC_GPU_CC_GMU_BCR		5

#define GPUCC_GPU_CC_GX_BCR		6

#define GPUCC_GPU_CC_XO_BCR		7

/* GPU_CC GDSCRs */

#define GPU_CX_GDSC			0

#define GPU_GX_GDSC			1

#endif