Loading arch/powerpc/include/asm/sstep.h +2 −0 Original line number Diff line number Diff line Loading @@ -97,6 +97,8 @@ enum instruction_type { #define SIZE(n) ((n) << 12) #define GETSIZE(w) ((w) >> 12) #define GETTYPE(t) ((t) & INSTR_TYPE_MASK) #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) struct instruction_op { Loading arch/powerpc/kernel/align.c +1 −1 Original line number Diff line number Diff line Loading @@ -339,7 +339,7 @@ int fix_alignment(struct pt_regs *regs) if (r < 0) return -EINVAL; type = op.type & INSTR_TYPE_MASK; type = GETTYPE(op.type); if (!OP_IS_LOAD_STORE(type)) { if (op.type != CACHEOP + DCBZ) return -EINVAL; Loading arch/powerpc/lib/sstep.c +3 −3 Original line number Diff line number Diff line Loading @@ -2642,7 +2642,7 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) unsigned long next_pc; next_pc = truncate_if_32bit(regs->msr, regs->nip + 4); switch (op->type & INSTR_TYPE_MASK) { switch (GETTYPE(op->type)) { case COMPUTE: if (op->type & SETREG) regs->gpr[op->reg] = op->val; Loading Loading @@ -2740,7 +2740,7 @@ int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op) err = 0; size = GETSIZE(op->type); type = op->type & INSTR_TYPE_MASK; type = GETTYPE(op->type); cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE); ea = truncate_if_32bit(regs->msr, op->ea); Loading Loading @@ -3002,7 +3002,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr) } err = 0; type = op.type & INSTR_TYPE_MASK; type = GETTYPE(op.type); if (OP_IS_LOAD_STORE(type)) { err = emulate_loadstore(regs, &op); Loading Loading
arch/powerpc/include/asm/sstep.h +2 −0 Original line number Diff line number Diff line Loading @@ -97,6 +97,8 @@ enum instruction_type { #define SIZE(n) ((n) << 12) #define GETSIZE(w) ((w) >> 12) #define GETTYPE(t) ((t) & INSTR_TYPE_MASK) #define MKOP(t, f, s) ((t) | (f) | SIZE(s)) struct instruction_op { Loading
arch/powerpc/kernel/align.c +1 −1 Original line number Diff line number Diff line Loading @@ -339,7 +339,7 @@ int fix_alignment(struct pt_regs *regs) if (r < 0) return -EINVAL; type = op.type & INSTR_TYPE_MASK; type = GETTYPE(op.type); if (!OP_IS_LOAD_STORE(type)) { if (op.type != CACHEOP + DCBZ) return -EINVAL; Loading
arch/powerpc/lib/sstep.c +3 −3 Original line number Diff line number Diff line Loading @@ -2642,7 +2642,7 @@ void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op) unsigned long next_pc; next_pc = truncate_if_32bit(regs->msr, regs->nip + 4); switch (op->type & INSTR_TYPE_MASK) { switch (GETTYPE(op->type)) { case COMPUTE: if (op->type & SETREG) regs->gpr[op->reg] = op->val; Loading Loading @@ -2740,7 +2740,7 @@ int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op) err = 0; size = GETSIZE(op->type); type = op->type & INSTR_TYPE_MASK; type = GETTYPE(op->type); cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE); ea = truncate_if_32bit(regs->msr, op->ea); Loading Loading @@ -3002,7 +3002,7 @@ int emulate_step(struct pt_regs *regs, unsigned int instr) } err = 0; type = op.type & INSTR_TYPE_MASK; type = GETTYPE(op.type); if (OP_IS_LOAD_STORE(type)) { err = emulate_loadstore(regs, &op); Loading