Commit e65deb79 authored by Stephen Boyd's avatar Stephen Boyd Committed by Wen Zhiwei
Browse files

clk: qcom: gcc-sm8550: Don't use parking clk_ops for QUPs 

stable inclusion
from stable-v6.6.51
commit a5e871d26ba182c2eb245761e90f6a8e8bad3001
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/IAYRVR

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a5e871d26ba182c2eb245761e90f6a8e8bad3001



--------------------------------

[ Upstream commit d10eeb75168b84ed9559c58efe2756c2e0bc052a ]

The QUPs aren't shared in a way that requires parking the RCG at an
always on parent in case some other entity turns on the clk. The
hardware is capable of setting a new frequency itself with the DFS mode,
so parking is unnecessary. Furthermore, there aren't any GDSCs for these
devices, so there isn't a possibility of the GDSC turning on the clks
for housekeeping purposes.

This wasn't a problem to mark these clks shared until we started parking
shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom:
Park shared RCGs upon registration"). Parking at init is actually
harmful to the UART when earlycon is used. If the device is pumping out
data while the frequency changes you'll see garbage on the serial
console until the driver can probe and actually set a proper frequency.

Revert the QUP part of commit 929c75d57566 ("clk: qcom: gcc-sm8550: Mark
RCGs shared where applicable") so that the QUPs don't get parked during
clk registration and break UART operations.

Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration")
Fixes: 929c75d57566 ("clk: qcom: gcc-sm8550: Mark RCGs shared where applicable")
Cc: Konrad Dybcio <konradybcio@kernel.org>
Cc: Bjorn Andersson <andersson@kernel.org>
Cc: Taniya Das <quic_tdas@quicinc.com>
Reported-by: default avatarAmit Pundir <amit.pundir@linaro.org>
Closes: https://lore.kernel.org/CAMi1Hd1KQBE4kKUdAn8E5FV+BiKzuv+8FoyWQrrTHPDoYTuhgA@mail.gmail.com


Signed-off-by: default avatarStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20240819233628.2074654-2-swboyd@chromium.org


Tested-by: default avatarAmit Pundir <amit.pundir@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
Signed-off-by: default avatarWen Zhiwei <wenzhiwei@kylinos.cn>
parent dc33dfe5

drivers/clk/qcom/gcc-sm8550.c

+26 −26
Original line number Diff line number Diff line
@@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = { 
		.parent_data = gcc_parent_data_0,

		.num_parents = ARRAY_SIZE(gcc_parent_data_0),

		.flags = CLK_SET_RATE_PARENT,

		.ops = &clk_rcg2_shared_ops,

		.ops = &clk_rcg2_ops,

	},

};
@@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
@@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
@@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
@@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
@@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
@@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
@@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
@@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
@@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
@@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
@@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
@@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
@@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
@@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
@@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = { 
	.parent_data = gcc_parent_data_8,

	.num_parents = ARRAY_SIZE(gcc_parent_data_8),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
@@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = { 
	.parent_data = gcc_parent_data_0,

	.num_parents = ARRAY_SIZE(gcc_parent_data_0),

	.flags = CLK_SET_RATE_PARENT,

	.ops = &clk_rcg2_shared_ops,

	.ops = &clk_rcg2_ops,

};



static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {