Commit e6580d0e authored by Alex Elder's avatar Alex Elder Committed by David S. Miller
Browse files

net: ipa: share field mask values for GSI interrupt type 



The GSI interrupt type register and interrupt type mask register
have the same field bits at the same locations.  Use a common set of
field masks for both registers rather than essentially duplicating
them.  The only place the interrupt mask register uses any of these
is in gsi_irq_enable().

Signed-off-by: default avatarAlex Elder <elder@linaro.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e0ebe204

drivers/net/ipa/gsi.c

+2 −2
Original line number Diff line number Diff line
@@ -254,8 +254,8 @@ static void gsi_irq_enable(struct gsi *gsi) 


	/* We don't use inter-EE channel or event interrupts */

	val = GSI_CNTXT_TYPE_IRQ_MSK_ALL;

	val &= ~MSK_INTER_EE_CH_CTRL_FMASK;

	val &= ~MSK_INTER_EE_EV_CTRL_FMASK;

	val &= ~INTER_EE_CH_CTRL_FMASK;

	val &= ~INTER_EE_EV_CTRL_FMASK;

	iowrite32(val, gsi->virt + GSI_CNTXT_TYPE_IRQ_MSK_OFFSET);



	val = GENMASK(gsi->channel_count - 1, 0);

drivers/net/ipa/gsi_reg.h

+5 −12
Original line number Diff line number Diff line
@@ -258,6 +258,11 @@ 
			GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(GSI_EE_AP)

#define GSI_EE_N_CNTXT_TYPE_IRQ_OFFSET(ee) \

			(0x0001f080 + 0x4000 * (ee))

#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \

			GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)

#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \

			(0x0001f088 + 0x4000 * (ee))

/* The masks below are used for the TYPE_IRQ and TYPE_IRQ_MASK registers */

#define CH_CTRL_FMASK			GENMASK(0, 0)

#define EV_CTRL_FMASK			GENMASK(1, 1)

#define GLOB_EE_FMASK			GENMASK(2, 2)
@@ -265,18 +270,6 @@ 
#define INTER_EE_CH_CTRL_FMASK		GENMASK(4, 4)

#define INTER_EE_EV_CTRL_FMASK		GENMASK(5, 5)

#define GENERAL_FMASK			GENMASK(6, 6)



#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \

			GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(GSI_EE_AP)

#define GSI_EE_N_CNTXT_TYPE_IRQ_MSK_OFFSET(ee) \

			(0x0001f088 + 0x4000 * (ee))

#define MSK_CH_CTRL_FMASK		GENMASK(0, 0)

#define MSK_EV_CTRL_FMASK		GENMASK(1, 1)

#define MSK_GLOB_EE_FMASK		GENMASK(2, 2)

#define MSK_IEOB_FMASK			GENMASK(3, 3)

#define MSK_INTER_EE_CH_CTRL_FMASK	GENMASK(4, 4)

#define MSK_INTER_EE_EV_CTRL_FMASK	GENMASK(5, 5)

#define MSK_GENERAL_FMASK		GENMASK(6, 6)

#define GSI_CNTXT_TYPE_IRQ_MSK_ALL	GENMASK(6, 0)



#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \