Commit e5f52102 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/trbe-errata' into for-next/core 

* for-next/trbe-errata:
  arm64: errata: Add detection for TRBE write to out-of-range
  arm64: errata: Add workaround for TSB flush failures
  arm64: errata: Add detection for TRBE overwrite in FILL mode
  arm64: Add Neoverse-N2, Cortex-A710 CPU part definition
parents 655ee557 8d81b2a3

Documentation/arm64/silicon-errata.rst

+12 −0
Original line number Diff line number Diff line
@@ -92,12 +92,24 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2067961        | ARM64_ERRATUM_2067961       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+115 −0
Original line number Diff line number Diff line
@@ -666,6 +666,121 @@ config ARM64_ERRATUM_1508412 


	  If unsure, say Y.



config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	bool



config ARM64_ERRATUM_2119858

	bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode"

	default y

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	depends on CORESIGHT_TRBE

	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2119858.



	  Affected Cortex-A710 cores could overwrite up to 3 cache lines of trace

	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in

	  the event of a WRAP event.



	  Work around the issue by always making sure we move the TRBPTR_EL1 by

	  256 bytes before enabling the buffer and filling the first 256 bytes of

	  the buffer with ETM ignore packets upon disabling.



	  If unsure, say Y.



config ARM64_ERRATUM_2139208

	bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"

	default y

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	depends on CORESIGHT_TRBE

	select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	help

	  This option adds the workaround for ARM Neoverse-N2 erratum 2139208.



	  Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace

	  data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in

	  the event of a WRAP event.



	  Work around the issue by always making sure we move the TRBPTR_EL1 by

	  256 bytes before enabling the buffer and filling the first 256 bytes of

	  the buffer with ETM ignore packets upon disabling.



	  If unsure, say Y.



config ARM64_WORKAROUND_TSB_FLUSH_FAILURE

	bool



config ARM64_ERRATUM_2054223

	bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"

	default y

	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE

	help

	  Enable workaround for ARM Cortex-A710 erratum 2054223



	  Affected cores may fail to flush the trace data on a TSB instruction, when

	  the PE is in trace prohibited state. This will cause losing a few bytes

	  of the trace cached.



	  Workaround is to issue two TSB consecutively on affected cores.



	  If unsure, say Y.



config ARM64_ERRATUM_2067961

	bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"

	default y

	select ARM64_WORKAROUND_TSB_FLUSH_FAILURE

	help

	  Enable workaround for ARM Neoverse-N2 erratum 2067961



	  Affected cores may fail to flush the trace data on a TSB instruction, when

	  the PE is in trace prohibited state. This will cause losing a few bytes

	  of the trace cached.



	  Workaround is to issue two TSB consecutively on affected cores.



	  If unsure, say Y.



config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	bool



config ARM64_ERRATUM_2253138

	bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	depends on CORESIGHT_TRBE

	default y

	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	help

	  This option adds the workaround for ARM Neoverse-N2 erratum 2253138.



	  Affected Neoverse-N2 cores might write to an out-of-range address, not reserved

	  for TRBE. Under some conditions, the TRBE might generate a write to the next

	  virtually addressed page following the last page of the TRBE address space

	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.



	  Work around this in the driver by always making sure that there is a

	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.



	  If unsure, say Y.



config ARM64_ERRATUM_2224489

	bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range"

	depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in

	depends on CORESIGHT_TRBE

	default y

	select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	help

	  This option adds the workaround for ARM Cortex-A710 erratum 2224489.



	  Affected Cortex-A710 cores might write to an out-of-range address, not reserved

	  for TRBE. Under some conditions, the TRBE might generate a write to the next

	  virtually addressed page following the last page of the TRBE address space

	  (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.



	  Work around this in the driver by always making sure that there is a

	  page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/barrier.h

+15 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ 
#define dsb(opt)	asm volatile("dsb " #opt : : : "memory")



#define psb_csync()	asm volatile("hint #17" : : : "memory")

#define tsb_csync()	asm volatile("hint #18" : : : "memory")

#define __tsb_csync()	asm volatile("hint #18" : : : "memory")

#define csdb()		asm volatile("hint #20" : : : "memory")



#ifdef CONFIG_ARM64_PSEUDO_NMI
@@ -46,6 +46,20 @@ 
#define dma_rmb()	dmb(oshld)

#define dma_wmb()	dmb(oshst)





#define tsb_csync()								\

	do {									\

		/*								\

		 * CPUs affected by Arm Erratum 2054223 or 2067961 needs	\

		 * another TSB to ensure the trace is flushed. The barriers	\

		 * don't have to be strictly back to back, as long as the	\

		 * CPU is in trace prohibited state.				\

		 */								\

		if (cpus_have_final_cap(ARM64_WORKAROUND_TSB_FLUSH_FAILURE))	\

			__tsb_csync();						\

		__tsb_csync();							\

	} while (0)



/*

 * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz

 * and 0 otherwise.

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -73,6 +73,8 @@ 
#define ARM_CPU_PART_CORTEX_A76		0xD0B

#define ARM_CPU_PART_NEOVERSE_N1	0xD0C

#define ARM_CPU_PART_CORTEX_A77		0xD0D

#define ARM_CPU_PART_CORTEX_A710	0xD47

#define ARM_CPU_PART_NEOVERSE_N2	0xD49



#define APM_CPU_PART_POTENZA		0x000
@@ -113,6 +115,8 @@ 
#define MIDR_CORTEX_A76	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)

#define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)

#define MIDR_CORTEX_A77	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)

#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)

#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)

#define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)

#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)

#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

arch/arm64/kernel/cpu_errata.c

+64 −0
Original line number Diff line number Diff line
@@ -340,6 +340,42 @@ static const struct midr_range erratum_1463225[] = { 
};

#endif



#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

static const struct midr_range trbe_overwrite_fill_mode_cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_2139208

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2119858

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

#endif

	{},

};

#endif	/* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */



#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE

static const struct midr_range tsb_flush_fail_cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_2067961

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2054223

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

#endif

	{},

};

#endif	/* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */



#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

static struct midr_range trbe_write_out_of_range_cpus[] = {

#ifdef CONFIG_ARM64_ERRATUM_2253138

	MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),

#endif

#ifdef CONFIG_ARM64_ERRATUM_2224489

	MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),

#endif

	{},

};

#endif /* CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE */



const struct arm64_cpu_capabilities arm64_errata[] = {

#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE

	{
@@ -533,6 +569,34 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_NVIDIA_CARMEL_CNP,

		ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),

	},

#endif

#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE

	{

		/*

		 * The erratum work around is handled within the TRBE

		 * driver and can be applied per-cpu. So, we can allow

		 * a late CPU to come online with this erratum.

		 */

		.desc = "ARM erratum 2119858 or 2139208",

		.capability = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE,

		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,

		CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus),

	},

#endif

#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE

	{

		.desc = "ARM erratum 2067961 or 2054223",

		.capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE,

		ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus),

	},

#endif

#ifdef CONFIG_ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

	{

		.desc = "ARM erratum 2253138 or 2224489",

		.capability = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE,

		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,

		CAP_MIDR_RANGE_LIST(trbe_write_out_of_range_cpus),

	},

#endif

	{

	}