Commit e5dfcd27 authored by Robin Chen's avatar Robin Chen Committed by Alex Deucher
Browse files

drm/amd/display: dc_link_set_psr_allow_active refactoring 



[Why]
To expose new power optimization flags to PSR interface. It allows the
PSR related power features can be enabled separately base on different
use scenarios.

Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarAgustin Gutierrez <agustin.gutierrez@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarRobin Chen <po-tchen@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 33df94e1

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c

+8 −2
Original line number Diff line number Diff line
@@ -107,6 +107,8 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 
	 */

	// Init fail safe of 2 frames static

	unsigned int num_frames_static = 2;

	unsigned int power_opt = 0;

	bool psr_enable = true;



	DRM_DEBUG_DRIVER("Enabling psr...\n");
@@ -133,7 +135,9 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 
					   &stream, 1,

					   &params);



	return dc_link_set_psr_allow_active(link, true, false, false);

	power_opt |= psr_power_opt_z10_static_screen;



	return dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);

}



/*
@@ -144,10 +148,12 @@ bool amdgpu_dm_psr_enable(struct dc_stream_state *stream) 
 */

bool amdgpu_dm_psr_disable(struct dc_stream_state *stream)

{

	unsigned int power_opt = 0;

	bool psr_enable = false;



	DRM_DEBUG_DRIVER("Disabling psr...\n");



	return dc_link_set_psr_allow_active(stream->link, false, true, false);

	return dc_link_set_psr_allow_active(stream->link, &psr_enable, true, false, &power_opt);

}



/*

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+4 −2
Original line number Diff line number Diff line
@@ -100,11 +100,13 @@ void clk_mgr_exit_optimized_pwr_state(const struct dc *dc, struct clk_mgr *clk_m 


	if (edp_num) {

		for (panel_inst = 0; panel_inst < edp_num; panel_inst++) {

			bool allow_active = false;



			edp_link = edp_links[panel_inst];

			if (!edp_link->psr_settings.psr_feature_enabled)

				continue;

			clk_mgr->psr_allow_active_cache = edp_link->psr_settings.psr_allow_active;

			dc_link_set_psr_allow_active(edp_link, false, false, false);

			dc_link_set_psr_allow_active(edp_link, &allow_active, false, false, NULL);

		}

	}
@@ -124,7 +126,7 @@ void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) 
			if (!edp_link->psr_settings.psr_feature_enabled)

				continue;

			dc_link_set_psr_allow_active(edp_link,

					clk_mgr->psr_allow_active_cache, false, false);

					&clk_mgr->psr_allow_active_cache, false, false, NULL);

		}

	}

drivers/gpu/drm/amd/display/dc/core/dc.c

+5 −2
Original line number Diff line number Diff line
@@ -3493,6 +3493,7 @@ void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_ 
bool dc_set_psr_allow_active(struct dc *dc, bool enable)

{

	int i;

	bool allow_active;



	for (i = 0; i < dc->current_state->stream_count ; i++) {

		struct dc_link *link;
@@ -3504,10 +3505,12 @@ bool dc_set_psr_allow_active(struct dc *dc, bool enable) 


		if (link->psr_settings.psr_feature_enabled) {

			if (enable && !link->psr_settings.psr_allow_active) {

				if (!dc_link_set_psr_allow_active(link, true, false, false))

				allow_active = true;

				if (!dc_link_set_psr_allow_active(link, &allow_active, false, false, NULL))

					return false;

			} else if (!enable && link->psr_settings.psr_allow_active) {

				if (!dc_link_set_psr_allow_active(link, false, true, false))

				allow_active = false;

				if (!dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL))

					return false;

			}

		}

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+26 −13
Original line number Diff line number Diff line
@@ -2916,8 +2916,8 @@ bool dc_link_set_backlight_level(const struct dc_link *link, 
	return true;

}



bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,

		bool wait, bool force_static)

bool dc_link_set_psr_allow_active(struct dc_link *link, const bool *allow_active,

		bool wait, bool force_static, const unsigned int *power_opts)

{

	struct dc  *dc = link->ctx->dc;

	struct dmcu *dmcu = dc->res_pool->dmcu;
@@ -2930,20 +2930,33 @@ bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, 
	if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))

		return false;



	link->psr_settings.psr_allow_active = allow_active;

	/* Set power optimization flag */

	if (power_opts && link->psr_settings.psr_power_opt != *power_opts) {

		link->psr_settings.psr_power_opt = *power_opts;



		if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)

			psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt);

	}



	/* Enable or Disable PSR */

	if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {

		link->psr_settings.psr_allow_active = *allow_active;



#if defined(CONFIG_DRM_AMD_DC_DCN)

	if (!allow_active)

		if (!link->psr_settings.psr_allow_active)

			dc_z10_restore(dc);

#endif



		if (psr != NULL && link->psr_settings.psr_feature_enabled) {

			if (force_static && psr->funcs->psr_force_static)

				psr->funcs->psr_force_static(psr, panel_inst);

		psr->funcs->psr_enable(psr, allow_active, wait, panel_inst);

	} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)

		dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);

			psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);

		} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&

			link->psr_settings.psr_feature_enabled)

			dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);

		else

			return false;

	}



	return true;

}

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+6 −2
Original line number Diff line number Diff line
@@ -3523,6 +3523,8 @@ static bool handle_hpd_irq_psr_sink(struct dc_link *link) 
		if (psr_error_status.bits.LINK_CRC_ERROR ||

				psr_error_status.bits.RFB_STORAGE_ERROR ||

				psr_error_status.bits.VSC_SDP_ERROR) {

			bool allow_active;



			/* Acknowledge and clear error bits */

			dm_helpers_dp_write_dpcd(

				link->ctx,
@@ -3532,8 +3534,10 @@ static bool handle_hpd_irq_psr_sink(struct dc_link *link) 
				sizeof(psr_error_status.raw));



			/* PSR error, disable and re-enable PSR */

			dc_link_set_psr_allow_active(link, false, true, false);

			dc_link_set_psr_allow_active(link, true, true, false);

			allow_active = false;

			dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL);

			allow_active = true;

			dc_link_set_psr_allow_active(link, &allow_active, true, false, NULL);



			return true;

		} else if (psr_sink_psr_status.bits.SINK_SELF_REFRESH_STATUS ==