Commit e5ce2f19 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'edac_updates_for_v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras 

Pull EDAC updates from Borislav Petkov:

 - amd64_edac: Add support for Zen4 client hardware

 - amd64_edac: Remove the version string as it is useless and actively
   confusing when looking at backported versions of the driver

 - Add a driver for the Nuvoton NPCM memory controller

 - A debugfs error checking cleanup

* tag 'edac_updates_for_v6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras:
  EDAC/npcm: Add NPCM memory controller driver
  dt-bindings: memory-controllers: nuvoton: Add NPCM memory controller
  EDAC/thunderx: Check debugfs file creation retval properly
  EDAC/amd64: Add support for ECC on family 19h model 60h-7Fh
  EDAC/amd64: Remove module version string
parents 88afbb21 852667c3

Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Nuvoton NPCM Memory Controller



maintainers:

  - Marvin Lin <kflin@nuvoton.com>

  - Stanley Chu <yschu@nuvoton.com>



description: |

  The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction

  check).



  The memory controller supports single bit error correction, double bit error

  detection (in-line ECC in which a section (1/8th) of the memory device used to

  store data is used for ECC storage).



  Note, the bootloader must configure ECC mode for the memory controller.



properties:

  compatible:

    enum:

      - nuvoton,npcm750-memory-controller

      - nuvoton,npcm845-memory-controller



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts



additionalProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/arm-gic.h>



    mc: memory-controller@f0824000 {

        compatible = "nuvoton,npcm750-memory-controller";

        reg = <0xf0824000 0x1000>;

        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;

    };

MAINTAINERS

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@@ -7494,6 +7494,14 @@ L: linux-edac@vger.kernel.org 
S:	Maintained

F:	drivers/edac/mpc85xx_edac.[ch]









EDAC-NPCM









M:	Marvin Lin <kflin@nuvoton.com>









M:	Stanley Chu <yschu@nuvoton.com>









L:	linux-edac@vger.kernel.org









S:	Maintained









F:	Documentation/devicetree/bindings/memory-controllers/nuvoton,npcm-memory-controller.yaml









F:	drivers/edac/npcm_edac.c

















EDAC-PASEMI









M:	Egor Martovetsky <egor@pasemi.com>









L:	linux-edac@vger.kernel.org
































drivers/edac/Kconfig



+11
−0






























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@@ -550,4 +550,15 @@ config EDAC_ZYNQMP







	  Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be









	  built as a module. In that case it will be called zynqmp_edac.



















config EDAC_NPCM









	tristate "Nuvoton NPCM DDR Memory Controller"









	depends on (ARCH_NPCM || COMPILE_TEST)









	help









	  Support for error detection and correction on the Nuvoton NPCM DDR









	  memory controller.



















	  The memory controller supports single bit error correction, double bit









	  error detection (in-line ECC in which a section 1/8th of the memory









	  device used to store data is used for ECC storage).



















endif # EDAC
























drivers/edac/Makefile



+1
−0






























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@@ -84,4 +84,5 @@ obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o







obj-$(CONFIG_EDAC_ASPEED)		+= aspeed_edac.o









obj-$(CONFIG_EDAC_BLUEFIELD)		+= bluefield_edac.o









obj-$(CONFIG_EDAC_DMC520)		+= dmc520_edac.o









obj-$(CONFIG_EDAC_NPCM)			+= npcm_edac.o









obj-$(CONFIG_EDAC_ZYNQMP)		+= zynqmp_edac.o
























drivers/edac/amd64_edac.c



+9
−3






























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@@ -3816,6 +3816,14 @@ static int per_family_init(struct amd64_pvt *pvt)







		case 0x50 ... 0x5f:









			pvt->ctl_name			= "F19h_M50h";









			break;









		case 0x60 ... 0x6f:









			pvt->ctl_name			= "F19h_M60h";









			pvt->flags.zn_regs_v2		= 1;









			break;









		case 0x70 ... 0x7f:









			pvt->ctl_name			= "F19h_M70h";









			pvt->flags.zn_regs_v2		= 1;









			break;









		case 0xa0 ... 0xaf:









			pvt->ctl_name			= "F19h_MA0h";









			pvt->max_mcs			= 12;








@@ -4074,8 +4082,6 @@ static int __init amd64_edac_init(void)







	amd64_err("%s on 32-bit is unsupported. USE AT YOUR OWN RISK!\n", EDAC_MOD_STR);









#endif



















	printk(KERN_INFO "AMD64 EDAC driver v%s\n", EDAC_AMD64_VERSION);



















	return 0;



















err_pci:








@@ -4121,7 +4127,7 @@ module_exit(amd64_edac_exit);

















MODULE_LICENSE("GPL");









MODULE_AUTHOR("SoftwareBitMaker: Doug Thompson, Dave Peterson, Thayne Harbaugh; AMD");









MODULE_DESCRIPTION("MC support for AMD64 memory controllers - " EDAC_AMD64_VERSION);









MODULE_DESCRIPTION("MC support for AMD64 memory controllers");



















module_param(edac_op_state, int, 0444);









MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");